# US 8,569,799 B2 · III-V semiconductor devices with buried contacts

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- Number: US 8,569,799 B2
- Document ID: US8569799B2
- Status: Granted
- Kind: B2
- Application number: 13/331,899
- Filed: 2011-12-20
- Published: 2013-06-20
- Granted: 2013-10-29
- Earliest claimed: 2011-12-20
- Assignees: Infineon Technologies Austria AG
- Applicants: Gilberto Curatola; Guanmauro Pozzovivo; Oliver Häberlen
- Inventors: Gilberto Curatola; Guanmauro Pozzovivo; Oliver Häberlen
- Web page: https://patentgrep.com/patent/US8569799B2

## CPC

- H10D 30/4755: {having wide bandgap charge-carrier supplying layers, e.g. modulation doped HEMTs such as n-AlGaAs/GaAs HEMTs}
- H10D 8/051: {of Schottky diodes}
- H10D 8/60: Schottky-barrier diodes
- H10D 30/015: {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT}
- H10D 62/824: comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10D 64/251: {Source or drain electrodes for field-effect devices}
- H10W 20/021: {of interconnections within wafers or substrates}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device such as a diode or transistor includes a semiconductor substrate, a first region of III-V semiconductor material on the semiconductor substrate and a second region of III-V semiconductor material on the first region. The second region is spaced apart from the semiconductor substrate by the first region. The second region is of a different composition than the first region. The semiconductor device further includes a buried contact extending from the semiconductor substrate to the second region through the first region. The buried contact electrically connects the second region to the semiconductor substrate.

## Claims

### Claim 1

A semiconductor device, comprising:
a semiconductor substrate;
a first region of III-V semiconductor material on the semiconductor substrate;
a second region of III-V semiconductor material on the first region with the second region spaced apart from the semiconductor substrate by the first region, the second region being of a different composition than the first region;
a buried contact extending from the semiconductor substrate to the second region through the first region, the buried contact electrically connecting the second region to the semiconductor substrate, wherein the buried contact has a first side contacting the semiconductor substrate and a second opposing side contacting the second region; and
a dielectric material extending from the second side of the buried contact toward a side of the second region facing away from the first region.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the first region is a nucleation layer and the second region comprises GaN.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the first region comprises AlN, the second region comprises AlxGa1-xN and 0<=x<1.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the semiconductor device is a diode further comprising:
a first conductive layer at a side of the second region facing away from the first region; and
a second conductive layer at a side of the semiconductor substrate facing away from the first region.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein the diode is operable to withstand voltages in the range of 300V to 1200V.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the semiconductor device is a transistor further comprising:
source and gate connections at a side of the second region facing away from the first region; and
a drain connection at a side of the semiconductor substrate facing away from the first region.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the second region comprises a more highly doped section adjacent the first region and a less highly doped section spaced apart from the first region by the more highly doped section, and wherein the buried contact electrically connects the more highly doped section to the semiconductor substrate.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, wherein the more highly doped section extends along the first region from the buried contact to an additional buried contact extending from the semiconductor substrate to the second region through the first region, the buried contacts being laterally spaced apart from one another by the more highly doped section.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein the buried contact comprises at least one of tungsten and doped polysilicon.

### Claim 10 (depends on 1)

The semiconductor device of claim 1, further comprising a third region of III-V semiconductor material on the second region, the third region having a band gap greater than a band gap of the second region and causing a 2-D electron gas (2DEG) in the second region.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, further comprising a fourth region of III-V semiconductor material on the third region so that the third region is interposed between the second region and the fourth region.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, further comprising:
a recess formed through the third and fourth regions; and
an electrode disposed in the recess and in contact with the second region, and wherein the 2DEG terminates under the electrode.

### Claim 13 (depends on 1)

The semiconductor device of claim 1, further comprising a third region of III-V semiconductor material interposed between the first and second regions, and wherein the buried contact extends from the semiconductor substrate to the second region through the first and third regions, the third region comprises a sequence of AlxGa1-xN layers with different Al content and 0<=x<=1.

### Claim 14

A method of manufacturing a semiconductor device, comprising:
forming a first region of III-V semiconductor material on a semiconductor substrate;
forming a second region of III-V semiconductor material on the first region so that the second region is spaced apart from the semiconductor substrate by the first region, the second region being of a different composition than the first region;
forming a buried contact extending from the semiconductor substrate to the second region through the first region, the buried contact electrically connecting the second region to the semiconductor substrate, wherein the buried contact has a first side contacting the semiconductor substrate and a second opposing side contacting the second region; and
forming a dielectric material extending from the second side of the buried contact toward a side of the second region facing away from the first region.

### Claim 15 (depends on 14)

The method of claim 14, wherein the semiconductor device is a diode and the method further comprises:
forming a first conductive layer at a side of the second region facing away from the first region; and
forming a second conductive layer at a side of the semiconductor substrate facing away from the first region.

### Claim 16 (depends on 14)

The method of claim 14, wherein the semiconductor device is a transistor and the method further comprises:
forming source and gate connections at a side of the second region facing away from the first region; and
forming a drain connection at a side of the semiconductor substrate facing away from the first region.

### Claim 17 (depends on 14)

The method of claim 14, wherein forming the first and second regions and the buried contact comprises:
epitaxially growing the first region on the semiconductor substrate;
epitaxially growing a more highly doped section of the second region on the first region;
etching an opening through the more highly doped section of the second region and through the first region to the substrate;
filling the opening with a conductive material to form the buried contact; and
epitaxially growing a less highly doped section of the second region on the more highly doped section after the buried contact is formed, including a lateral overgrowth of the less highly doped section over the buried contact.

### Claim 18 (depends on 14)

The method of claim 14, wherein forming the first and second regions and the buried contact comprises:
epitaxially growing the first region on the semiconductor substrate;
epitaxially growing the second region on the first region, the second region including a more highly doped section towards the first region and a less highly doped section on the more highly doped section;
etching an opening through the first and second regions to the substrate;
filling the opening with a conductive material;
recessing the conductive material below a junction between the less highly doped section of the second region and the more highly doped section to form the buried contact and a residual opening in the second region above the buried contact; and
filling the residual opening with the dielectric material.

### Claim 19 (depends on 14)

The method of claim 14, wherein forming the second region comprises forming a more highly doped section contacting the first region and a less highly doped section above the more highly doped section, and wherein the buried contact electrically connects the more highly doped section to the semiconductor substrate.

### Claim 20 (depends on 19)

The method of claim 19, further comprising forming an additional buried contact extending from the semiconductor substrate to the second region through the first region, the more highly doped section of the second region extending along the first region from the buried contact to the additional buried contact so that the buried contacts are laterally spaced apart from one another by the more highly doped section.

### Claim 21 (depends on 14)

The method of claim 14, further comprising forming a third region of III-V semiconductor material on the second region, the third region having a band gap greater than the band gap of the second region and causing a 2-D electron gas (2DEG) in the second region.

### Claim 22 (depends on 21)

The method of claim 21, further comprising forming a fourth region of III-V semiconductor material on the third region so that the third region is interposed between the second region and the fourth region.

### Claim 23 (depends on 22)

The method of claim 22, further comprising:
forming a recess through the third and fourth regions; and
forming an electrode in the recess and in contact with the second region, and wherein the 2DEG terminates under the electrode.

### Claim 24 (depends on 14)

The method of claim 14, further comprising forming a third region of III-V semiconductor material interposed between the first and second regions, and wherein the buried contact extends from the semiconductor substrate to the second region through the first and third regions, the third region comprises a sequence of AlxGa1-xN layers with different Al content and 0<=x<=1.