# US 8,569,795 B2 · Semiconductor device and method of manufacturing the same

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- Number: US 8,569,795 B2
- Document ID: US8569795B2
- Status: Granted
- Kind: B2
- Application number: 13/217,472
- Filed: 2011-08-25
- Published: 2012-09-13
- Granted: 2013-10-29
- Earliest claimed: 2011-03-10
- Assignees: Kabushiki Kaisha Toshiba
- Applicants: Hiroshi Kono; Yukio Nakabayashi; Takashi Shinohe; Makoto Mizukami
- Inventors: Hiroshi Kono; Yukio Nakabayashi; Takashi Shinohe; Makoto Mizukami
- Web page: https://patentgrep.com/patent/US8569795B2

## CPC

- H10D 30/66: Vertical DMOS [VDMOS] FETs
- H10D 12/031: {of IGBTs}
- H10D 30/0291: {of vertical DMOS [VDMOS] FETs}
- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 62/8325: {Silicon carbide}
- H10D 64/01366: {the semiconductor being silicon carbide}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 62/107: {Buried supplementary regions, e.g. buried guard rings (multi-RESURF H10D62/111)}
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10D 64/669: {the conductor further comprising additional layers of alloy material, compound material or organic material, e.g. TaN/TiAlN}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device of an embodiment includes: a silicon carbide substrate including first and second principal surfaces; a first conductive-type first silicon carbide layer provided on the first principal surface of the silicon carbide substrate; a second conductive-type first silicon carbide region formed on a surface of the first silicon carbide layer; a first conductive-type second silicon carbide region formed on a surface of the first silicon carbide region; a second conductive-type third silicon carbide region formed on the surface of the first silicon carbide region; a gate insulating film continuously formed on the surfaces of the first silicon carbide layer, the first silicon carbide region, and the second silicon carbide region; a first electrode formed of silicon carbide formed on the gate insulating film; a second electrode formed on the first electrode; an interlayer insulating film for covering the first and second electrodes; a third electrode electrically connected to the second silicon carbide region and the third silicon carbide region; and a fourth electrode formed on the second principal surface of the silicon carbide substrate.

## Claims

### Claim 1

A semiconductor device, comprising:
a silicon carbide substrate including first and second principal surfaces;
a first conductive-type first silicon carbide layer provided on the first principal surface of the silicon carbide substrate;
a second conductive-type first silicon carbide region formed on a surface of the first silicon carbide layer;
a first conductive-type second silicon carbide region formed on a surface of the first silicon carbide region;
a second conductive-type third silicon carbide region formed on the surface of the first silicon carbide region;
a gate insulating film continuously formed on the surfaces of the first silicon carbide layer, the first silicon carbide region, and the second silicon carbide region;
a first electrode formed of silicon carbide formed on the gate insulating film;
a second electrode formed on the first electrode;
an interlayer insulating film for covering the first and second electrodes;
a third electrode electrically connected to the second silicon carbide region and the third silicon carbide region; and
a fourth electrode formed on the second principal surface of the silicon carbide substrate;
wherein the second silicon carbide region is adjacent to the third silicon carbide region.

### Claim 2 (depends on 1)

The device according to claim 1, wherein the first electrode is formed of poly SiC or amorphous SiC.

### Claim 3 (depends on 1)

The device according to claim 1, wherein the first electrode is formed of poly SiC or amorphous SiC whose work function is 4.0 eV or lower.

### Claim 4 (depends on 1)

The device according to claim 1, wherein the second electrode is any of at least one of metals of Ni, Mo, Al, W, V, Co, and Ti, for example, metal silicide of the metal, mixture of the metal and the metal silicide of the metal, graphite, and graphene.

### Claim 5 (depends on 1)

The device according to claim 1, wherein the fourth electrode is any of at least one of metals of Ni, Mo, Al, W, V, Co, and Ti, for example, metal silicide of the metal, mixture of the metal and the metal silicide of the metal, graphite and graphene.

### Claim 6 (depends on 1)

The device according to claim 1, further comprising: a trench formed by etching the first silicon carbide layer, the first silicon carbide region, and the second silicon carbide region.

### Claim 7 (depends on 6)

The device according to claim 6, wherein the first electrode is formed in the trench and on a part of the surface of the second silicon carbide region.

### Claim 8 (depends on 6)

The device according to claim 6, wherein a second conductive-type fourth silicon carbide region is formed on a bottom of the trench.

### Claim 9 (depends on 6)

The device according to claim 6, wherein the gate insulating film, the first electrode, and the second electrode are provided in the trench.

### Claim 10 (depends on 1)

The device according to claim 1, wherein a contact anneal process is simultaneously performed to the second electrode formed on the first electrode formed of the silicon carbide on the gate insulating film and the third electrode formed on the second and third silicon carbide regions.

### Claim 11 (depends on 10)

The device according to claim 10, wherein a temperature of the contact anneal is not lower than 800° C. and not higher than 1000° C.