# US 8,569,769 B2 · E-mode high electron mobility transistors and methods of manufacturing the same

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- Number: US 8,569,769 B2
- Document ID: US8569769B2
- Status: Granted
- Kind: B2
- Application number: 13/179,859
- Filed: 2011-07-11
- Published: 2012-05-10
- Granted: 2013-10-29
- Earliest claimed: 2010-11-05
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: In-jun Hwang; Ki-ha Hong; Jong-seob Kim; Jae-Kwang Shin; Jae-joon Oh; Jong-bong Ha; Hyuk-soon Choi
- Inventors: In-jun Hwang; Ki-ha Hong; Jong-seob Kim; Jae-Kwang Shin; Jae-joon Oh; Jong-bong Ha; Hyuk-soon Choi
- Web page: https://patentgrep.com/patent/US8569769B2

## CPC

- H10D 30/015: {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT}
- H10D 30/4755: {having wide bandgap charge-carrier supplying layers, e.g. modulation doped HEMTs such as n-AlGaAs/GaAs HEMTs}
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10D 64/411: {for FETs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

An Enhancement-mode (E-mode) high electron mobility transistor (HEMT) includes a channel layer with a 2-Dimensional Electron Gas (2DEG), a barrier layer inducing the 2DEG in the channel layer, source and drain electrodes on the barrier layer, a depletion layer on the barrier layer between the source and drain electrodes, and a gate electrode on the depletion layer. The barrier layer is recessed below the gate electrode and the depletion layer covers a surface of the recess and extends onto the barrier layer around the recess.

## Claims

### Claim 1

A High Electron Mobility Transistor (HEMT), comprising:
a channel layer including a 2-Dimensional Electron Gas (2DEG);
a barrier layer configured to induce the 2DEG in the channel layer, the barrier layer including a recess region,
the barrier layer including a first barrier layer on the channel layer and a second barrier layer on the first barrier layer;
source and drain electrodes on the barrier layer;
a depletion layer on the barrier layer between the source and drain electrodes, the depletion layer covering a surface of the barrier layer in the recess region and extending onto a region of the barrier layer outside the recess region,
the depletion layer including at least one of a GaN layer, an InN layer, an AlGaN layer, an AlInN layer, an InGaN layer and an AlInGaN layer; and
a gate electrode on the depletion layer in the recess region,
wherein a polarization rate of the second barrier layer is greater than a polarization rate of the first barrier layer.

### Claim 2 (depends on 1)

The HEMT of claim 1, wherein a thickness of the barrier layer in the recess region is about 5 nm to about 20 nm.

### Claim 3 (depends on 1)

The HEMT of claim 1, wherein the barrier layer is at least one of an AlN layer, an AlGaN layer, an AlInN layer and an AlInGaN layer.

### Claim 4 (depends on 1)

The HEMT of claim 1, wherein the depletion layer is a p-doped layer.

### Claim 5 (depends on 1)

The HEMT of claim 1, wherein the gate electrode includes at least one of a p-metal and a nitride.

### Claim 6 (depends on 1)

The HEMT of claim 1, wherein the depletion layer contacts sidewalls of the gate electrode, and at least one of the source and drain electrodes.

### Claim 7

A method of manufacturing a high electron mobility transistor (HEMT), the method comprising:
forming a channel layer;
forming a barrier layer to induce a two-dimensional electron gas (2DEG) in the channel layer, the barrier layer including a first barrier layer on the channel layer and a second barrier layer on the first barrier layer;
forming a recess in the barrier layer;
forming a depletion layer to cover a surface of the barrier layer in the recess and to extend onto regions of the barrier layer adjacent to the recess,
the depletion layer including at least one of a GaN layer, an InN layer, an AlGaN layer, an AlInN layer, an InGaN layer and an AlInGaN layer;
forming source and drain electrodes on the barrier layer; and
forming a gate electrode on the depletion layer,
wherein a polarization rate of the second barrier layer is greater than a polarization rate of the first barrier layer.

### Claim 8 (depends on 7)

The method of claim 7, further comprising:
sequentially-stacking a seed layer and a buffer layer on a substrate,
wherein the forming a channel layer includes forming the channel layer on the buffer layer.

### Claim 9 (depends on 7)

The method of claim 7, wherein the forming a barrier layer includes forming the barrier layer to a thickness of about 20 nm to about 100 nm.

### Claim 10 (depends on 7)

The method of claim 7, wherein forming a recess in the barrier layer includes recessing the barrier layer to a thickness of about 5 nm to about 20 nm.

### Claim 11 (depends on 7)

The method of claim 7, wherein the forming a recess includes removing a portion of the second barrier layer corresponding to the gate electrode.

### Claim 12 (depends on 7)

The method of claim 7, wherein the forming source and drain electrodes includes forming the source and drain electrodes a distance apart from the depletion layer.

### Claim 13 (depends on 7)

The method of claim 7, wherein the depletion layer contacts sidewalls of the gate electrode, and at least one of the source and drain electrodes.

### Claim 14

A method of manufacturing a high electron mobility transistor (HEMT), the method comprising:
forming a channel layer;
forming a first barrier layer to induce a two-dimensional electron gas (2DEG) in the channel layer;
forming a depletion layer pattern on the first barrier layer;
growing a second barrier layer on the first barrier layer around the depletion layer pattern;
forming source and drain electrodes on the second barrier layer; and
forming a gate electrode on the depletion layer pattern.

### Claim 15 (depends on 14)

The method of claim 14, wherein the forming a depletion layer pattern includes:
forming a depletion layer covering a top surface of the first barrier layer; and
patterning the depletion layer to form the depletion layer pattern.

### Claim 16 (depends on 14)

The method of claim 14, wherein the forming a first barrier layer includes forming the first barrier layer to a thickness of about 5 nm to about 20 nm.

### Claim 17 (depends on 14)

The method of claim 14, wherein the growing a second barrier layer includes growing the second barrier layer to a thickness of about 20 nm to about 100 nm.

### Claim 18 (depends on 15)

The method of claim 15, wherein the growing the second barrier layer includes growing the second barrier layer until an uppermost surface of the second barrier layer is level with an uppermost surface of the depletion layer.