# US 8,569,764 B2 · Thin film transistor, method of fabricating the same, and organic light emitting diode display device including the same

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- Number: US 8,569,764 B2
- Document ID: US8569764B2
- Status: Granted
- Kind: B2
- Application number: 12/045,172
- Filed: 2008-03-10
- Published: 2008-09-11
- Granted: 2013-10-29
- Earliest claimed: 2007-03-09
- Assignees: Samsung Display Co., Ltd.
- Applicants: Byoung-Keon Park; Tae-hoon Yang; Jin-Wook Seo; Sei-Hwan Jung; Ki-Yong Lee
- Inventors: Byoung-Keon Park; Tae-hoon Yang; Jin-Wook Seo; Sei-Hwan Jung; Ki-Yong Lee
- Web page: https://patentgrep.com/patent/US8569764B2

## CPC

- H10D 30/6711: {by using electrodes contacting the supplementary regions or layers}
- H10D 86/00: Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D 86/0225: {using crystallisation-promoting species, e.g. using a Ni catalyst}
- H10K 59/12: Active-matrix OLED [AMOLED] displays
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES

## Abstract

A thin film transistor includes: a substrate; a semiconductor layer disposed on the substrate, and including a channel region, source and drain regions, and edge regions having a first impurity formed at edges of the source and drain regions, and optionally, in the channel region; a gate insulating layer insulating the semiconductor layer; a gate electrode insulated from the semiconductor layer by the gate insulating layer; and source and drain electrodes electrically connected to the semiconductor layer.

## Claims

### Claim 1

A thin film transistor, comprising:
a substrate;
a semiconductor layer disposed on the substrate, and comprising a crystallization inducing metal, a channel region, source and drain regions respectively disposed on opposing first and second sides of the channel region, and edge regions that are doped with a first impurity and that extend continuously from the source region to the drain region, along opposing third and fourth sides of the channel region, and excluding center portions of the channel region, source region and drain region;
a gate insulating layer insulating the semiconductor layer;
a gate electrode insulated from the semiconductor layer by the gate insulating layer; and
source and drain electrodes electrically connected to the semiconductor layer,
wherein a first interconnection is formed through a first contact hole exposing the source region and a portion of the edge regions at edges of the source region,
wherein a second interconnection is formed through a second contact hole exposing the drain region and a portion of the edge regions at edges of the drain region, and
wherein the first impurity is doped at a dose of 1*e11/cm3 to 3*e15/cm3 to getter the crystallization inducing metal into the edge regions of the semiconductor layer.

### Claim 2 (depends on 1)

The thin film transistor according to claim 1, wherein the first impurity comprises phosphorous (P).

### Claim 3 (depends on 1)

The thin film transistor according to claim 1, wherein the first interconnection is the source electrode and the second interconnection is the drain electrode.

### Claim 4 (depends on 1)

The thin film transistor according to claim 1, wherein the crystallization inducing metal comprises at least one selected from the group consisting of Ni, Pd, Ti, Ag, Au, Al, Sn, Sb, Cu, Co, Mo, Tr, Ru, Rh, Cd and Pt.

### Claim 5 (depends on 1)

The thin film transistor according to claim 1, wherein the concentration of the crystallization inducing metal in the channel region of the semiconductor layer is less than 1*e16/cm3.

### Claim 6

An organic light emitting diode (OLED) display device, comprising:
a substrate;
a semiconductor layer disposed on the substrate, and comprising a crystallization inducing metal, a channel region, source and drain regions respectively disposed on opposing first and second sides of the channel, and edge regions that are doped with a first impurity and that extend continuously from the source region to the drain region, along opposing third and fourth sides of the channel region, and excluding center portions of the channel region, source region and drain region;
a gate insulating layer insulating the semiconductor layer;
a gate electrode insulated from the semiconductor layer by the gate insulating layer;
source and drain electrodes electrically connected to the semiconductor layer;
a first electrode electrically connected to one of the source and drain electrodes; and
an organic layer and a second electrode disposed on the first electrode,
wherein a first interconnection is formed through a first contact hole exposing the source region and a portion of the edge regions at edges of the source region,
wherein a second interconnection is formed through a second contact hole exposing the drain region and a portion of the edge regions at edges of the drain region, and
wherein the first impurity is doped at a dose of 1*e11cm3 to 3*e15/cm3 to getter the crystallization inducing metal into the edge regions of the semiconductor layer.

### Claim 7 (depends on 6)

The OLED display device according to claim 6, wherein the first impurity comprises phosphorous (P).

### Claim 8 (depends on 6)

The OLED display device according to claim 6, wherein the first interconnection is the source electrode and the second interconnection is the drain electrode.

### Claim 9 (depends on 6)

The OLED display device according to claim 6, wherein the concentration of the crystallization inducing metal in the channel region of the semiconductor layer is less than 1*e16/cm3.