# US 8,569,757 B2 · Semiconductor device with amorphous silicon MAS memory cell structure and manufacturing method thereof

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- Number: US 8,569,757 B2
- Document ID: US8569757B2
- Status: Granted
- Kind: B2
- Application number: 13/333,994
- Filed: 2011-12-21
- Published: 2012-04-19
- Granted: 2013-10-29
- Earliest claimed: 2008-07-02
- Assignees: Semiconductor Manufacturing International (Shanghai) Corporation
- Applicants: Mieno Fumitake
- Inventors: Mieno Fumitake
- Web page: https://patentgrep.com/patent/US8569757B2

## CPC

- H10D 30/69: IGFETs having charge trapping gate insulators, e.g. MNOS transistors
- H10B 43/30: characterised by the memory core region
- H10D 8/812: {Charge-trapping diodes}
- H10D 86/00: Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A semiconductor device with an amorphous silicon (a-Si) metal-aluminum oxide-semiconductor (MAS) memory cell structure. The device includes a substrate, a dielectric layer overlying the substrate, and one or more source or drain regions embedded in the dielectric layer with a co-planar surface of n-type a-Si and the dielectric layer. Additionally, the device includes a p-i-n a-Si diode junction. The device further includes an aluminum oxide charge trapping layer on the a-Si p-i-n diode junction and a metal control gate overlying the aluminum oxide layer. A method is provided for making the a-Si MAS memory cell structure and can be repeated to integrate the structure three-dimensionally.

## Claims

### Claim 1

A device with amorphous silicon (a-Si) metal-aluminum oxide-semiconductor (MAS) memory cell structure, the device comprising:
a substrate;
a dielectric layer on the substrate, the dielectric layer being associated with a first surface;
one or more source or drain regions being embedded in the dielectric layer, each of the one or more source or drain regions being associated with a second surface and including an n-type a-Si layer, a diffusion barrier layer, and a conductive layer, the n-type a-Si layer being located on the diffusion barrier layer, the diffusion barrier layer overlying the conductive layer, the second surface consisting of n-type a-Si and being substantially co-planar with the first surface;
an i-type a-Si layer overlying the surface of the n-type a-Si and the dielectric layer;
a p-type a-Si layer overlying the i-type a-Si layer;
an aluminum oxide layer on the p-type a-Si layer; and
at least one control gate overlying the aluminum oxide layer.

### Claim 2 (depends on 1)

The device of claim 1, wherein the dielectric layer comprises silicon dioxide.

### Claim 3 (depends on 1)

The device of claim 1, wherein the conductive layer is metal silicide comprising TiSi2.

### Claim 4 (depends on 3)

The device of claim 3, wherein the metal silicide layer is capable of coupling with memory array bitlines electrically.

### Claim 5 (depends on 1)

The device of claim 1, wherein the diffusion barrier layer is metal-nitride comprising TiN.

### Claim 6 (depends on 1)

The device of claim 1, wherein the p-type a-Si layer overlying the i-type a-Si layer is capable of forming an amorphous silicon p-i-n diode junction at the second surface.

### Claim 7 (depends on 1)

The device of claim 1, wherein the p-type a-Si layer overlying the i-type a-Si layer is capable of forming a p-channel connecting the n-type a-Si source region and the n-type a-Si drain region.

### Claim 8 (depends on 1)

The device of claim 1 further comprising a dielectric barrier layer between the p-type a-Si layer and the aluminum oxide layer.

### Claim 9 (depends on 8)

The device of claim 8, wherein the aluminum oxide layer is capable of trapping charges tunneled through the dielectric barrier layer for memory storage.

### Claim 10 (depends on 1)

The device of claim 1 wherein the control gate is characterized by a metal layer pattern overlying the aluminum oxide layer.

### Claim 11 (depends on 10)

The device of claim 10, wherein the metal layer comprises aluminum or titanium.

### Claim 12 (depends on 10)

The device of claim 10, wherein the metal layer couples with memory array wordlines electrically.

### Claim 13 (depends on 10)

The device of claim 10, wherein the control gate is positioned over at least one source and one drain region.