# US 8,569,741 B2 · Electronic arrangements for passivated silicon nanowires

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 8,569,741 B2
- Document ID: US8569741B2
- Status: Granted
- Kind: B2
- Application number: 13/286,008
- Filed: 2011-10-31
- Published: 2012-11-01
- Granted: 2013-10-29
- Earliest claimed: 2009-06-26
- Assignees: California Institute of Technology
- Applicants: Axel Scherer; Sameer Walavalkar; Michael D. Henry; Andrew P. Homyk
- Inventors: Axel Scherer; Sameer Walavalkar; Michael D. Henry; Andrew P. Homyk
- Web page: https://patentgrep.com/patent/US8569741B2

## CPC

- H10D 62/118: {Nanostructure semiconductor bodies}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- B82Y 40/00: Manufacture or treatment of nanostructures
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 62/122: {oriented at angles to substrates, e.g. perpendicular to substrates}
- H10D 64/205: {Nanosized electrodes, e.g. nanowire electrodes}
- H10H 20/818: within the light-emitting regions
- Y10S 977/762: Nanowire or quantum wire, i.e. axially elongated structure having two dimensions of 100 nm or less
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- H10H: INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- Y10S: TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

## Abstract

Methods for fabricating passivated silicon nanowires and an electronic arrangement thus obtained are described. Such arrangements may comprise a metal-oxide-semiconductor (MOS) structure such that the arrangements may be utilized for MOS field-effect transistors (MOSFETs) or opto-electronic switches.

## Claims

### Claim 1

An electronic arrangement comprising:
a plurality of insulator covered semiconductor nanoscale pillar structures substantially perpendicular to a planar surface;
a conductive layer coated on the insulator covered semiconductor nanoscale pillar structures, wherein the conductive layer and the insulator layer are devoid of an end portion thereof, so that end portions of the nanoscale pillar structures are electrically accessible;
the arrangement further comprising:
a dielectric material coated on the planar surface; and
a further conductive layer coated on the dielectric material and accessible portions of the nanoscale pillar structures, wherein direct contact between the conductive layer and the further conductive layer is absent, and wherein the insulator covered semiconductor nanoscale pillar structures extend inside the further conductive layer.

### Claim 2 (depends on 1)

The arrangement of claim 1, wherein the plurality of nanoscale pillar structures is located on a substrate.

### Claim 3 (depends on 2)

The arrangement of claim 2, wherein the semiconductor nanoscale pillar structures and the substrate are made of silicon.

### Claim 4 (depends on 2)

The arrangement of claim 2, wherein a conductive backside contact is coated on a backside of the substrate, opposite the nanoscale pillar structures.

### Claim 5 (depends on 1)

The arrangement of claim 1, said arrangement being a metal-oxide-semiconductor (MOS) arrangement.

### Claim 6 (depends on 5)

The arrangement of claim 5, said arrangement being a field-effect transistor (FET).

### Claim 7 (depends on 6)

The arrangement of claim 6, said conductive layer being a gate of the FET.

### Claim 8 (depends on 7)

The arrangement of claim 7, wherein the plurality of the nanoscale pillars is located on a substrate, said substrate and said further conductive layer being a source and a drain or respectively a drain and a source of the FET.

### Claim 9

An electronic arrangement comprising:
an insulator covered semiconductor substrate;
a plurality of nanoscale pillar structures on the substrate, substantially perpendicular to a planar surface; and
a conductive layer covering the insulator and the nanoscale pillar structures, wherein the conductive layer is devoid of an end portion thereof, so that end portions of the nanoscale pillar structures are electrically accessible;
a dielectric material coated on a planar surface;
a further conductive layer coated on the dielectric material and accessible portions of the nanoscale pillar structures, wherein direct contact between the conductive layer and the further conductive layer is absent, and wherein the nanoscale pillar structures extend inside the further conductive layer.

### Claim 10 (depends on 9)

The arrangement of claim 9, said arrangement being a metal-semiconductor (MES) arrangement.

### Claim 11 (depends on 10)

The arrangement of claim 10, wherein the arrangement is a MESFET.

### Claim 12

An electronic arrangement comprising:
a plurality of insulator covered semiconductor nanoscale pillar structures substantially perpendicular to a planar surface, wherein the insulator layer is devoid of an end portion thereof, so that end portions of the nanoscale pillar structures are electrically accessible;
the arrangement further comprising:
a dielectric material coated on the planar surface; and
a further conductive layer coated on the dielectric material and accessible portions of the nanoscale pillar structures, wherein the semiconductor nanoscale pillar structures extend inside the further conductive layer, and wherein the insulator layer does not extend inside the further conductive layer.