# US 8,569,734 B2 · Forming resistive random access memories together with fuse arrays

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- Number: US 8,569,734 B2
- Document ID: US8569734B2
- Status: Granted
- Kind: B2
- Application number: 12/849,864
- Filed: 2010-08-04
- Published: 2012-02-09
- Granted: 2013-10-29
- Earliest claimed: 2010-08-04
- Assignees: Micron Technology, Inc.
- Applicants: Andrea Redaelli; Agostino Pirevano; Umberto M. Meotto; Giorgio Servalli
- Inventors: Andrea Redaelli; Agostino Pirevano; Umberto M. Meotto; Giorgio Servalli
- Web page: https://patentgrep.com/patent/US8569734B2

## CPC

- H10N 70/063: {by etching of pre-deposited switching material layers, e.g. lithography}
- H10B 63/32: {of the bipolar type}
- H10B 63/80: {Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays}
- H10N 70/011: {Manufacture or treatment of multistable switching devices}
- H10N 70/066: {by filling of openings, e.g. damascene method}
- H10N 70/231: {based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect}
- H10N 70/801: {Constructional details of multistable switching devices}
- H10N 70/823: {adapted for essentially horizontal current flow, e.g. bridge type devices}
- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- H10N 70/8413: {adapted for resistive heating}
- H10N 70/8828: {Tellurides, e.g. GeSbTe}
- H10W 20/493: {Fuses, i.e. interconnections changeable from conductive to non-conductive}
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A resistive random access memory array may be formed on the same substrate with a fuse array. The random access memory and the fuse array may use the same active material. For example, both the fuse array and the memory array may use a chalcogenide material as the active switching material. The main array may use a pattern of perpendicular sets of trench isolations and the fuse array may only use one set of parallel trench isolations. As a result, the fuse array may have a conductive line extending continuously between adjacent trench isolations. In some embodiments, this continuous line may reduce the resistance of the conductive path through the fuses.

## Claims

### Claim 1

A method comprising:
forming a chalcogenide memory array using a first set of steps including forming select devices by forming two sets of orthogonal trenches; and
forming a fuse array at the same time on the same substrate using the first set of steps including only forming one set of said trenches in the fuse array to form conductive lines.

### Claim 2 (depends on 1)

The method of claim 1 including forming address lines transverse to said conductive lines, said address lines including only one fuse per line.

### Claim 3 (depends on 2)

The method of claim 2 including forming interrupted address lines wherein said address lines include a gap, each address line including a first portion on one side of said gap and a second portion on the opposite side of the said gap.

### Claim 4 (depends on 3)

The method of claim 3 including forming fuses only on one of said first or second portions of said address lines.

### Claim 5 (depends on 4)

The method of claim 4 including forming fuses at the intersection of an address line and a conductive line and forming some of said address line portions to be shorter than others so that some of said address line portions do not overlap a conductive line.

### Claim 6

A method comprising:
forming a chalcogenide memory array with a first set of parallel trenches and a second set of parallel trenches perpendicular to said first set of parallel trenches; and
forming a fuse array on the same substrate with said chalcogenide memory array and forming said first set of parallel trenches to extend into said fuse array.

### Claim 7 (depends on 6)

The method of claim 6 including forming address lines including only one fuse per line.

### Claim 8 (depends on 7)

The method of claim 7 including forming interrupted address lines wherein said address lines include a gap, each address line including a first portion on one side of said gap and a second portion on the opposite side of said gap.

### Claim 9 (depends on 8)

The method of claim 8 including forming fuses only on one of said first or second portions of said address lines.

### Claim 10 (depends on 9)

The method of claim 9 including forming fuses at an intersection of an address line and a conductive line and forming some of said address line portions shorter than others of said address lines so that some of said address line portions do not overlap a conductive line.

### Claim 11

An integrated circuit comprising:
a semiconductor substrate;
a chalcogenide memory array formed on said substrate, said chalcogenide memory array including a first set of parallel trenches and a second set of parallel trenches perpendicular to said first set of parallel trenches; and
a fuse array on said substrate, said first set of parallel trenches extending into said fuse array.

### Claim 12 (depends on 11)

The circuit of claim 11, said fuse array including address lines and including only one fuse per address line.

### Claim 13 (depends on 12)

The circuit of claim 12 including said address lines including gaps where said address lines include a first portion on one side of said gap and a second portion on the opposite side of said gap.

### Claim 14 (depends on 13)

The circuit of claim 13 including said fuses only being positioned on one of said first or second portions of said address lines.

### Claim 15 (depends on 14)

The circuit of claim 14 wherein said fuses are formed at the intersection of an address line and a conductive line and some of said address line portions being shorter than others so that some of said address line portions do not overlap a conductive line.

### Claim 16 (depends on 14)

The circuit of claim 14 wherein said circuit is a phase change memory.