# US 8,569,733 B2 · Semiconductor memory device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,569,733 B2 - Document ID: US8569733B2 - Status: Granted - Kind: B2 - Application number: 13/314,527 - Filed: 2011-12-08 - Published: 2012-06-14 - Granted: 2013-10-29 - Earliest claimed: 2010-12-14 - Assignees: Kabushiki Kaisha Toshiba - Applicants: Nobuaki Yasutake - Inventors: Nobuaki Yasutake - Web page: https://patentgrep.com/patent/US8569733B2 ## CPC - H10N 70/841: {Electrodes} - H10B 63/20: {comprising selection components having two electrodes, e.g. diodes} - H10B 63/84: {arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays} - H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR - H10B: ELECTRONIC MEMORY DEVICES ## Abstract A memory cell comprises a diode layer, a variable resistance layer, a first electrode layer. The diode layer functions as a rectifier element. The variable resistance layer functions as a variable resistance element. The first electrode layer is provided between the variable resistance layer and the diode layer. The first electrode layer comprises a titanium nitride layer configured by titanium nitride. Where a first ratio is defined as a ratio of titanium atoms to nitrogen atoms in a first region in the titanium nitride layer and a second ratio is defined as a ratio of titanium atoms to nitrogen atoms in a second region which is in the titanium nitride layer and is nearer to the variable resistance layer than is the first region, the second ratio is larger than the first ratio. ## Claims ### Claim 1 A semiconductor memory device, comprising memory cells each disposed between a first line and a second line and each having a rectifier element and a variable resistance element connected in series, each of the memory cells comprising: a diode layer functioning as the rectifier element; a variable resistance layer functioning as the variable resistance element; and a first electrode layer provided between the variable resistance layer and the diode layer, the first electrode layer comprising a titanium nitride layer configured by titanium nitride, and, when a first ratio is defined as a ratio of titanium atoms to nitrogen atoms in a first region in the titanium nitride layer and a second ratio is defined as a ratio of titanium atoms to nitrogen atoms in a second region which is in the titanium nitride layer and is nearer to the variable resistance layer than is the first region, the second ratio being larger than the first ratio. ### Claim 2 (depends on 1) The semiconductor memory device according to claim 1, wherein the titanium nitride layer comprises: a first titanium nitride layer configured to have more nitrogen atoms than titanium atoms in a unit volume; and a second titanium nitride layer provided between the first titanium nitride layer and the variable resistance layer and configured to have more titanium atoms than nitrogen atoms in a unit volume. ### Claim 3 (depends on 1) The semiconductor memory device according to claim 1, wherein the titanium nitride layer is configured such that the ratio of titanium atoms to nitrogen atoms in the titanium nitride layer gradually reduces as a position thereof is closer to the diode layer than the variable resistance layer. ### Claim 4 (depends on 1) The semiconductor memory device according to claim 1, wherein the titanium nitride layer has a film thickness of 10 nm or less. ### Claim 5 (depends on 1) The semiconductor memory device according to claim 1, wherein the diode layer comprises: a first semiconductor layer having N type conductive property; and a second semiconductor layer having P type conductive property and provided between the first semiconductor layer and the first electrode layer, and a concentration of N type impurities included in the first semiconductor layer is 1×1020 atms/cm3 or more. ### Claim 6 (depends on 5) The semiconductor memory device according to claim 5, wherein a concentration of P type impurities included in the second semiconductor layer is 1×1020 atms/cm3 or more. ### Claim 7 (depends on 5) The semiconductor memory device according to claim 5, wherein the diode layer further comprises an intrinsic semiconductor layer provided between the first semiconductor layer and the second semiconductor layer. ### Claim 8 (depends on 1) The semiconductor memory device according to claim 1, wherein the first electrode layer further comprises a silicide layer provided between the titanium nitride layer and the diode layer. ### Claim 9 (depends on 8) The semiconductor memory device according to claim 8, wherein the silicide layer is configured by titanium silicide. ### Claim 10 (depends on 1) The semiconductor memory device according to claim 1, wherein each of the memory cells further comprises a second electrode layer provided between the first line and the diode layer. ### Claim 11 (depends on 10) The semiconductor memory device according to claim 10, wherein the second electrode layer is configured by titanium nitride. ### Claim 12 (depends on 11) The semiconductor memory device according to claim 11, wherein the second electrode layer has a film thickness of 10 nm or less. ### Claim 13 (depends on 1) The semiconductor memory device according to claim 1, wherein each of the memory cells further comprises a second electrode layer provided between the second line and the variable resistance layer. ### Claim 14 (depends on 13) The semiconductor memory device according to claim 13, wherein the second electrode layer is configured by titanium nitride. ### Claim 15 (depends on 14) The semiconductor memory device according to claim 14, wherein the second electrode layer has a film thickness of 10 nm or less. ### Claim 16 (depends on 1) The semiconductor memory device according to claim 1, wherein the variable resistance layer is configured by hafnium oxide. ### Claim 17 (depends on 1) The semiconductor memory device according to claim 1, wherein the first line is configured by any of tungsten, tungsten silicide, nickel silicide, or cobalt silicide. ### Claim 18 (depends on 1) The semiconductor memory device according to claim 1, wherein the second line is configured by any of tungsten, tungsten silicide, nickel silicide, or cobalt silicide. ### Claim 19 (depends on 1) The semiconductor memory device according to claim 1, wherein the second line is shared by a pair of memory cells positioned above and below the second line. ### Claim 20 (depends on 1) The semiconductor memory device according to claim 1, further comprising: a memory cell array including a plurality of the memory cells; and a peripheral circuit configured to control the memory cell array, wherein the peripheral circuit is positioned directly below the memory cell array.