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US 8,569,171 B2Granted
Mask-based silicidation for FEOL defectivity reduction and yield boost
AssigneeGlobalfoundries Inc.
InventorDmytro Chumakov
Life of this patent
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Abstract
A semiconductor device with reduced defect density is fabricated by forming localized metal silicides instead of full area silicidation. Embodiments include forming a transistor having a gate electrode and source/drain regions on a substrate, forming a masking layer with openings exposing portions of both the gate electrode and source/drain regions over the substrate, depositing metal in the openings on the exposed portions, forming silicides in the openings, and removing unreacted metal and the masking layer.
Claims16
A method comprising:
- forming a transistor on a substrate, the transistor having a gate electrode and source/drain regions;
- forming a masking layer over the substrate, the masking layer having openings exposing portions of the gate electrode and portions of the source/drain regions;
- depositing a metal in the openings on the exposed portions of the gate electrode and source/drain regions;
- forming metal silicide on the exposed portions of the gate electrode and source/drain regions;
- and
- removing unreacted metal and completely removing the masking layer,
- wherein the masking layer is formed by:
- forming an inter level dielectric (ILD) on the substrate, the ILD covering the transistor and having a substantially planar upper surface above an upper surface of the gate electrode;
- forming a lithographic mask on the ILD, the lithographic mask having openings corresponding to the exposed portions of the gate electrode and the source/drain regions;
- forming trenches in the ILD through the lithographic mask corresponding to the openings;
- and
- removing the lithographic mask.
9 more elements
A method comprising:
- forming one or more gate electrodes on a substrate, each gate electrode having spacers on opposite sides thereof;
- forming source/drain regions in the substrate on opposite sides of each gate electrode;
- forming an inter level dielectric (ILD) on the source/drain regions and the gate electrodes, the ILD covering the source/drain regions and the gate electrodes and having a substantially planar upper surface above an upper surface of the gate electrodes;
- forming a lithographic mask on the ILD, the lithographic mask having openings;
- aligning the openings of the lithographic mask with portions of the gate electrode and portions of the source/drain regions, the portions being less than 100% of the entire gate electrode and source/drain regions, respectively;
- etching trenches in the ILD through the lithographic mask corresponding to the openings, the trenches having a width of 10 nanometer (nm) to 100 nm and an aspect ratio of 1:1 to 100:1;
- removing the lithographic mask;
- depositing a metal in the trenches;
- annealing the metal to form metal silicide in the trenches;
- and
- removing unreacted metal and completely removing the ILD.
8 more elements
Dependencies are inferred from the claim text.