# US 8,569,170 B2 · Manufacturing method of semiconductor device comprising silicide layer with varied thickness > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,569,170 B2 - Document ID: US8569170B2 - Status: Granted - Kind: B2 - Application number: 12/636,811 - Filed: 2009-12-14 - Published: 2010-04-15 - Granted: 2013-10-29 - Earliest claimed: 2005-12-02 - Assignees: Semiconductor Energy Laboratory Co., Ltd. - Applicants: Hiromichi Godo; Hajime Tokunaga - Inventors: Hiromichi Godo; Hajime Tokunaga - Web page: https://patentgrep.com/patent/US8569170B2 ## CPC - H10D 30/6737: {characterised by the electrode materials} - H10D 30/0212: {using self-aligned silicidation} - H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes} - H10D 30/6743: {Silicon} - H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling} - H10D 86/01: Manufacture or treatment - H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)} - H10W 70/656: Fan-in layouts - H10W 72/5522: {comprising gold [Au]} - H10W 72/884: {Die-attach connectors and bond wires} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract It is an object of the present invention to obtain a transistor with a high ON current including a silicide layer without increasing the number of steps. A semiconductor device comprising the transistor includes a first region in which a thickness is increased from an edge on a channel formation region side and a second region in which a thickness is more uniform than that of the first region. The first and second region are separated by a line which is perpendicular to a horizontal line and passes through a point where a line, which passes through the edge of the silicide layer and forms an angle θ (0°<θ<45°) with the horizontal line, intersects with an interface between the silicide layer and an impurity region, and the thickness of the second region to a thickness of a silicon film is 0.6 or more. ## Claims ### Claim 1 A manufacturing method of a semiconductor device, comprising the steps of: forming a gate insulating film over a silicon film; forming a gate electrode over the gate insulating film; selectively exposing the silicon film by selectively removing the gate insulating film; forming a metal film in contact with a surface of the exposed silicon film so that a thickness of the metal film is thinnest on a side surface of the gate insulating film and continuously increased until reaching an outer side surface of the exposed silicon film; and forming a silicide layer in the silicon film by performing heat treatment on the metal film, wherein the silicide layer is formed so as to include a first region in which a thickness of the silicide layer is increased and a second region in which a thickness of the silicide layer is uniform. ### Claim 2 (depends on 1) The manufacturing method of a semiconductor device according to claim 1, wherein the heat treatment is conducted by a rapid thermal annealing. ### Claim 3 (depends on 1) The manufacturing method of a semiconductor device according to claim 1, wherein the heat treatment is conducted under reduced pressure or vacuum atmosphere. ### Claim 4 (depends on 1) The manufacturing method of a semiconductor device according to claim 1, wherein the silicon film is a crystalline silicon film. ### Claim 5 (depends on 1) The manufacturing method of a semiconductor device according to claim 1, wherein the silicide layer is formed so as to have an angle which is larger than 0° and smaller than 45° between an upper surface of the silicide layer and a first line which passes through an edge of the silicide layer and a point where a second line which perpendicularly crosses with the upper surface of the silicide layer and divides the silicide layer into the first region and the second region. ### Claim 6 (depends on 1) The manufacturing method of a semiconductor device according to claim 1, wherein a thickness of the second region to a thickness of the silicon film is 0.6 or more in ratio. ### Claim 7 A manufacturing method of a semiconductor device, comprising the steps of: forming a silicon film over a substrate with an insulating layer interposed therebetween; forming an insulating film over the silicon film; forming a gate electrode over the insulating film; forming an impurity region in the silicon film by adding an impurity element; selectively exposing the silicon film by selectively removing the insulating film; forming a metal film in contact with a surface of the exposed silicon film so that a thickness of the metal film is thinnest on a side surface of the insulating film and continuously increased until reaching an outer side surface of the exposed silicon film; and forming a silicide layer in the silicon film by performing heat treatment on the metal film, wherein the silicide layer is formed so as to include a first region in which a thickness of the silicide layer is increased and a second region in which a thickness of the silicide layer is uniform. ### Claim 8 (depends on 7) The manufacturing method of a semiconductor device according to claim 7, wherein the heat treatment is conducted by a rapid thermal annealing. ### Claim 9 (depends on 7) The manufacturing method of a semiconductor device according to claim 7, wherein the heat treatment is conducted under reduced pressure or vacuum atmosphere. ### Claim 10 (depends on 7) The manufacturing method of a semiconductor device according to claim 7, wherein the silicon film is a crystalline silicon film. ### Claim 11 (depends on 7) The manufacturing method of a semiconductor device according to claim 7, wherein the silicide layer is formed so as to have an angle which is larger than 0° and smaller than 45° between an upper surface of the silicide layer and a first line which passes through an edge of the silicide layer and a point where a second line which perpendicularly crosses with the upper surface of the silicide layer and divides the silicide layer into the first region and the second region. ### Claim 12 (depends on 7) The manufacturing method of a semiconductor device according to claim 7, wherein a thickness of the second region to a thickness of the silicon film is 0.6 or more in ratio. ### Claim 13 A manufacturing method of a semiconductor device, comprising the steps of: forming an amorphous silicon film over a substrate with an insulating layer interposed therebetween; crystallizing the amorphous silicon film to form a crystalline silicon film; forming an insulating film over the crystalline silicon film; forming an impurity region in the crystalline silicon film; selectively exposing the crystalline silicon film by selectively removing the insulating film; forming a metal film in contact with a surface of the exposed crystalline silicon film so that a thickness of the metal film is thinnest on a side surface of the insulating film and continuously increased until reaching an outer side surface of the exposed crystalline silicon film; and forming a silicide layer in the crystalline silicon film by performing heat treatment on the metal film, wherein the silicide layer is formed so as to include a first region in which a thickness of the silicide layer is increased and a second region in which a thickness of the silicide layer is uniform. ### Claim 14 (depends on 13) The manufacturing method of a semiconductor device according to claim 13, wherein the heat treatment is conducted by a rapid thermal annealing. ### Claim 15 (depends on 13) The manufacturing method of a semiconductor device according to claim 13, wherein the heat treatment is conducted under reduced pressure or vacuum atmosphere. ### Claim 16 (depends on 13) The manufacturing method of a semiconductor device according to claim 13, wherein the silicide layer is formed so as to have an angle which is larger than 0° and smaller than 45° between an upper surface of the silicide layer and a first line which passes through an edge of the silicide layer and a point where a second line which perpendicularly crosses with the upper surface of the silicide layer and divides the silicide layer into the first region and the second region. ### Claim 17 (depends on 13) The manufacturing method of a semiconductor device according to claim 13, wherein a thickness of the second region to a thickness of the crystalline silicon film is 0.6 or more in ratio.