Back to results
US 8,569,169 B2Granted
Bottom source power MOSFET with substrateless and manufacturing method thereof
AssigneeAlpha and Omega Semiconductor Incorporated
InventorsYueh-Se Ho, Yan Xun Xue, Ping Huang
Life of this patent
Estimating the term…
Abstract
A bottom source power metal-oxide-semiconductor field-effect transistor (MOSFET) device includes a gate electrode and a source electrode formed on an initial insulation layer on a first surface of a semiconductor chip and a drain electrode formed on a second surface of the semiconductor chip. The source electrode includes a source metal, a source electrode bump formed on the source metal and a source electrode metal layer on top of the source electrode bump. A first insulation layer covers the gate electrode. A through via aligned to the gate electrode is formed from the second surface of the chip to expose a portion of the gate electrode from the second surface.
Claims8
A manufacturing method of a bottom source power MOSFET device comprising:
- forming a gate metal and a source metal at a first surface of a semiconductor chip, the gate metal and the source metal being electrically insulated from each other, wherein forming the gate metal and source metal at the first surface of the semiconductor chip further comprising:
- forming an initial insulation layer on a substrate of the semiconductor chip;
- and
- depositing a metal layer on top of the initial insulation layer and patterning the metal layer into the gate metal and the source metal;
- forming a source electrode bump on the source metal by
- depositing a first insulation layer encapsulating the gate metal and an edge portion of the source metal, and electrode plating a metal onto the source metal exposed through the first insulation layer;
- depositing a dielectric material overlaying the gate metal and part of the source metal not covered by the source electrode bump, a surface of the dielectric material being coplanar to a surface of the source electrode bump;
- forming a source electrode metal layer overlaying the surface of the source electrode bump and the surface of the dielectric layer, wherein the source electrode metal layer being ready for connecting to the external devices;
- grinding the semiconductor chip from its second surface to reduce its thickness;
- depositing a drain metal layer on the second surface of the semiconductor chip;
- forming a through via above the gate metal from the second surface of the semiconductor chip to expose a portion of the gate metal;
- and
- forming an insulation layer covering a side wall of the through via;
- wherein the step of depositing the dielectric material overlaying the gate metal and part of the source metal not covered by the source electrode bump further comprising depositing a molding compound to cover the first insulation layer and the source electrode bump, and removing a portion of the molding compound to expose the surface of the source electrode bump.
11 more elements
A manufacturing method of a bottom source power MOSFET device comprising:
- forming a gate metal and a source metal at a first surface of a semiconductor chip, the gate metal and the source metal being electrically insulated from each other;
- forming a source electrode bump on the source metal;
- depositing a dielectric material overlaying the gate metal and part of the source metal not covered by the source electrode bump, a surface of the dielectric material being coplanar to a surface of the source electrode bump;
- forming a source electrode metal layer overlaying the surface of the source electrode bump and the surface of the dielectric layer, wherein the source electrode metal layer being ready for connecting to the external devices;
- grinding the semiconductor chip from its second surface to reduce its thickness;
- depositing a drain metal layer on the second surface of the semiconductor chip;
- forming a through via above the gate metal from the second surface of the semiconductor chip to expose a portion of the gate metal;
- and
- forming an insulation layer covering a side wall of the through via;
- wherein selected portions of the drain metal layer, the substrate of the semiconductor chip and the initial insulation layer being removed via laser drilling to form the through via.
7 more elements
A manufacturing method of a bottom source power MOSFET device comprising:
- forming a gate metal and a source metal at a first surface of a semiconductor chip, the gate metal and the source metal being electrically insulated from each other;
- forming a source electrode bump on the source metal;
- depositing a dielectric material overlaying the gate metal and part of the source metal not covered by the source electrode bump, a surface of the dielectric material being coplanar to a surface of the source electrode bump;
- forming a source electrode metal layer overlaying the surface of the source electrode bump and the surface of the dielectric layer, wherein the source electrode metal layer being ready for connecting to the external devices;
- grinding the semiconductor chip from its second surface to reduce its thickness;
- depositing a drain metal layer on the second surface of the semiconductor chip;
- forming a through via above the gate metal from the second surface of the semiconductor chip to expose a portion of the gate metal;
- and
- forming an insulation layer covering a side wall of the through via;
- wherein the step of forming a through via above the gate metal from the second surface of the semiconductor chip to expose a portion of the gate metal comprising:
- applying a first mask on the top surface of the drain metal layer, the first mask including an opening corresponding to the position of the gate electrode;
- and
- removing portions of the drain metal layer, the substrate of the semiconductor chip and the initial insulation layer through the opening by wet or dry etching to form the through via.
10 more elements
Dependencies are inferred from the claim text.