Device fabrication

A method for device fabrication, comprising:

• forming a first part of an integrated circuit (IC) at a first fabrication facility, the IC initially comprises a front-end-of-the-line (FEOL) circuitry die formed on a base wafer using a FEOL circuitry fabrication process;
• and
• forming a second part of the IC at a second fabrication facility, the second part comprises one or more layers of memory that are directly fabricated above each FEOL circuitry die using a back-end-of-the-line (BEOL) memory fabrication process,
• wherein after the forming of the first part and the second part, the IC comprises a unitary die including a base layer with active circuitry fabricated thereon and the one or more layers of memory in contact with and positioned above the base layer and electrically coupled with at least a portion of the active circuitry.

A method for device fabrication, comprising:

• forming a first part of an integrated circuit (IC) that initially comprises a front-end-of-the-line (FEOL) circuitry die formed on a base wafer using a FEOL circuitry fabrication process;
• and
• forming a second part of the IC, the second part comprises one or more layers of memory that are directly fabricated above the FEOL circuitry die using a back-end-of-the-line (BEOL) memory fabrication process,
• wherein after the forming of the first part and the second part, the IC comprises a unitary die including a base layer having active circuitry fabricated thereon and the one or more layers of memory fabricated directly above and in contact with the base layer and electrically coupled with at least a portion of the active circuitry.