# US 8,569,159 B2 · CMOS structure including non-planar hybrid orientation substrate with planar gate electrodes and method for fabrication > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,569,159 B2 - Document ID: US8569159B2 - Status: Granted - Kind: B2 - Application number: 13/453,215 - Filed: 2012-04-23 - Published: 2012-08-09 - Granted: 2013-10-29 - Earliest claimed: 2008-02-28 - Assignees: International Business Machines Corporation - Applicants: Kangguo Cheng - Inventors: Kangguo Cheng - Web page: https://patentgrep.com/patent/US8569159B2 ## CPC - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 30/751: {having composition variations in the channel regions} - H10D 84/0167: {Manufacturing their channels} - H10D 84/0177: {the gate conductors having different materials or different implants} - H10D 84/83135: {the IGFETs characterised by having different gate conductor materials or different gate conductor implants} - H10D 84/85: Complementary IGFETs, e.g. CMOS - H10D 30/0212: {using self-aligned silicidation} - H10D 30/798: {being provided in or under the channel regions} - H10D 64/01314: {the conductor comprising a layer of Ge, C or of compounds of Si, Ge or C contacting the insulator} - H10D 64/01316: {the conductor comprising a layer of elemental metal contacting the insulator, e.g. Ta, W, Mo or Al} - H10D 64/68: characterised by the insulator, e.g. by the gate insulator - H10D 84/0181: {Manufacturing their gate insulating layers} - H10D 84/8311: {the IGFETs characterised by having different channel structures} - H10D 84/83138: {the IGFETs characterised by having different shapes or dimensions of their gate conductors} - H10D 84/8314: {the IGFETs characterised by having gate insulating layers with different properties} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A semiconductor structure and a method for fabricating the semiconductor structure include a hybrid orientation substrate having a first active region having a first crystallographic orientation that is vertically separated from a second active region having a second crystallographic orientation different than the first crystallographic orientation. A first field effect device having a first gate electrode is located and formed within and upon the first active region and a second field effect device having a second gate electrode is located and formed within and upon the second active region. Upper surfaces of the first gate electrode and the second gate electrode are coplanar. The structure and method allow for avoidance of epitaxial defects generally encountered when using hybrid orientation technology substrates that include coplanar active regions. ## Claims ### Claim 1 A semiconductor structure comprising: a substrate comprising a first active region including a first crystallographic orientation material and a second active region including a second crystallographic orientation material, wherein a first upper surface of the first crystallographic orientation material is vertically offset and located beneath a second upper surface of the second crystallographic orientation material, wherein the second crystallographic orientation material is different than the first crystallographic orientation material; an isolation region located between the first active device region and the second active device region, wherein said isolation region has a topmost that is vertically offset and located above a recessed surface of the isolation region, wherein said topmost surface of said isolation region is coplanar with said second upper surface of the second crystallographic orientation material; and a p-type field effect transistor including a first gate located within the first active region and an n-type field effect transistor including a second gate located within the second active region, where an upper surface of the first gate and an upper surface of the second gate are coplanar, and a first gate dielectric of the first gate is in direct contact with the first upper surface, and a second gate dielectric of the second gate is in direct contact with the second upper surface. ### Claim 2 (depends on 1) The semiconductor structure of claim 1, wherein the first gate comprises a first gate material and the second gate comprises a second gate material different than the first gate material. ### Claim 3 (depends on 1) The semiconductor structure of claim 1, wherein the substrate comprises a bulk semiconductor substrate. ### Claim 4 (depends on 1) The semiconductor structure of claim 1, wherein the substrate comprises a semiconductor-on-insulator substrate. ### Claim 5 (depends on 1) The semiconductor structure of claim 1, wherein at least one of the first gate and the second gate comprises a silicon material. ### Claim 6 (depends on 1) The semiconductor structure of claim 1, wherein at least one of the first gate and the second gate comprises a metal material. ### Claim 7 (depends on 1) The semiconductor structure of claim 1, wherein the first crystallographic orientation material comprises silicon having a (110) and the second crystalline orientation material comprises silicon germanium. ### Claim 8 (depends on 1) The semiconductor structure of claim 1, wherein the first crystallographic orientation material comprises silicon germanium and the second crystalline orientation material comprises silicon having a (100) orientation. ### Claim 9 (depends on 1) The semiconductor structure of claim 1, further comprising a spacer material having a sidewall surface located on a vertical sidewall of said isolation region and a base surface located on said recessed surface of said isolation region. ### Claim 10 (depends on 1) The semiconductor structure of claim 1, wherein said recessed surface of the isolation region is coplanar with said first upper surface of the first crystallographic orientation material. ### Claim 11 A semiconductor structure comprising: a substrate comprising a first active region including a first crystallographic orientation material and a second active region including a second crystallographic orientation material, wherein a first upper surface of the first crystallographic orientation material is vertically offset and located beneath a second upper surface of the second crystallographic orientation material, wherein the second crystallographic orientation material has a different crystalline orientation than the first crystallographic orientation material; an isolation region located between the first active device region and the second active device region, wherein said isolation region has a topmost that is vertically offset and located above a recessed surface of the isolation region, wherein said topmost surface of said isolation region is coplanar with said second upper surface of the second crystallographic orientation material; and a p-type field effect transistor including a first gate located within the first active region and an n-type field effect transistor including a second gate located within the second active region, where an upper surface of the first gate and an upper surface of the second gate are coplanar, and a first gate dielectric of the first gate is in direct contact with the first upper surface, and a second gate dielectric of the second gate is in direct contact with the second upper surface. ### Claim 12 (depends on 11) The semiconductor structure of claim 11, wherein the first gate comprises a first gate material and the second gate comprises a second gate material different than the first gate material. ### Claim 13 (depends on 11) The semiconductor structure of claim 11, wherein the substrate comprises a bulk semiconductor substrate. ### Claim 14 (depends on 11) The semiconductor structure of claim 11, wherein the substrate comprises a semiconductor-on-insulator substrate. ### Claim 15 (depends on 11) The semiconductor structure of claim 11, wherein at least one of the first gate and the second gate comprises a silicon material. ### Claim 16 (depends on 11) The semiconductor structure of claim 11, wherein at least one of the first gate and the second gate comprises a metal material. ### Claim 17 (depends on 11) The semiconductor structure of claim 11, further comprising a spacer material having a sidewall surface located on a vertical sidewall of said isolation region and a base surface located on said recessed surface of said isolation region. ### Claim 18 (depends on 11) The semiconductor structure of claim 11, wherein said recessed surface of the isolation region is coplanar with said first upper surface of the first crystallographic orientation material.