# US 8,569,154 B2 · Three dimensional integration and methods of through silicon via creation

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- Number: US 8,569,154 B2
- Document ID: US8569154B2
- Status: Granted
- Kind: B2
- Application number: 13/422,415
- Filed: 2012-03-16
- Published: 2012-07-26
- Granted: 2013-10-29
- Earliest claimed: 2010-01-14
- Assignees: International Business Machines Corporation
- Applicants: Mukta G. Farooq; Emily R. Kinser; Richard Wise; Hakeem Yusuff
- Inventors: Mukta G. Farooq; Emily R. Kinser; Richard Wise; Hakeem Yusuff
- Web page: https://patentgrep.com/patent/US8569154B2

## CPC

- H10W 20/036: {the barrier, adhesion or liner layers being within a main fill metal}
- H10P 50/267: {using plasmas}
- H10P 76/4085: {characterised by the processes involved to create the masks}
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/0234: {comprising etching via holes that stop on pads or on electrodes}
- H10W 20/0242: {comprising etching via holes from the back sides of the chips, wafers or substrates}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/2134: {TSVs extending from the semiconductor wafer into back-end-of-line layers}
- H10W 90/00: Package configurations
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method includes patterning a photoresist layer on a structure to define an opening and expose a first planar area on a sacrificial substrate layer, etching to the exposed first planar area to form a cavity having a first depth in the structure, removing a portion of the photoresist to increase the size of the opening to define a second planar area on the sacrificial substrate layer, forming a doped portion in the sacrificial substrate layer, and etching the cavity to increase the depth of the cavity to expose a first conductor in the structure and to increase the planar area and depth of a portion of the cavity to expose a second conductor in the structure.

## Claims

### Claim 1

A method comprising:
patterning a photoresist layer on a structure to define an opening and expose a first planar area on a sacrificial substrate layer, the exposed first planar area aligned vertically with a first conductor embedded in the structure;
etching to the exposed first planar area to form a cavity having a first depth in the structure;
removing a portion of the photoresist to increase the size of the opening to define a second planar area on the sacrificial substrate layer;
forming a doped portion in the sacrificial substrate layer, the doped portion aligned vertically with a second conductor embedded in the structure different from the first conductor;
etching the cavity to increase the depth of the cavity, the first conductor being exposed in response to the etching of the cavity; and
etching the doped portion to expose an underlying planar area, and etching the underlying planar area to increase the planar area and depth of a portion of the cavity, the second conductor being exposed in response to increasing the planar area and depth.

### Claim 2 (depends on 1)

The method of claim 1, wherein the structure includes a first wafer and a second wafer.

### Claim 3 (depends on 1)

The method of claim 1, wherein the structure includes a first chip and a second chip.

### Claim 4 (depends on 1)

The method of claim 1, wherein the portion of exposed sacrificial substrate layer in the structure is doped with ions deposited at an oblique angle.

### Claim 5 (depends on 4)

The method of claim 4, wherein the oblique angle is between 95 degrees and 175 degrees.

### Claim 6 (depends on 1)

The method of claim 1, wherein the method
further comprises: removing the photoresist layer, the sacrificial substrate layer, and an optical planarization layer;
forming a dielectric portion in the cavity;
removing a portion of the dielectric layer;
depositing a barrier layer on the dielectric layer;
filling the cavity with a conductive material; and
removing the excess conductive material by planarization.

### Claim 7 (depends on 6)

The method of claim 6, wherein the conductive material is operative to electrically connect the first conductor to the second conductor.