# US 8,569,150 B2 · Method for producing a semiconductor device with a semiconductor body

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 8,569,150 B2
- Document ID: US8569150B2
- Status: Granted
- Kind: B2
- Application number: 13/085,196
- Filed: 2011-04-12
- Published: 2011-08-04
- Granted: 2013-10-29
- Earliest claimed: 2008-03-20
- Assignees: Infineon Technologies Austria AG
- Applicants: Armin Willmeroth; Franz Hirler
- Inventors: Armin Willmeroth; Franz Hirler
- Web page: https://patentgrep.com/patent/US8569150B2

## CPC

- H10D 30/66: Vertical DMOS [VDMOS] FETs
- H10D 62/111: {Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures}
- H10D 62/157: {Impurity concentrations or distributions}
- H10D 30/0295: {using recessing of the source electrodes}
- H10D 30/831: {Vertical FETs having PN junction gate electrodes (Vertical SIT H10D30/202)}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D 64/516: {the thicknesses being non-uniform}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device with a semiconductor body and method for its production is disclosed. The semiconductor body includes drift zones of epitaxially grown semiconductor material of a first conduction type. The semiconductor body further includes charge compensation zones of a second conduction type complementing the first conduction type, which are arranged laterally adjacent to the drift zones. The charge compensation zones are provided with a laterally limited charge compensation zone doping, which is introduced into the epitaxially grown semiconductor material. The epitaxially grown semiconductor material includes 20 to 80 atomic % of the doping material of the drift zones and a doping material balance of 80 to 20 atomic % introduced by ion implantation and diffusion.

## Claims

### Claim 1

A method for the production of a semiconductor device with a semiconductor body having drift zones of a first conduction type and charge compensation zones of a complementary conduction type, the method comprising:
a) providing a semiconductor wafer as a semiconductor substrate;
b) applying an epitaxial layer in a first epitaxial growth phase, during which the semiconductor material is in the process of epitaxial growth doped on the semiconductor wafer with 20 to 80 atomic % of a total implanted doping material of the first conduction type;
c) unmasked ion implantation of doping material of the first conduction type for the near-surface introduction of a doping material balance of 80 to 20 atomic % of the total dopant implanted into the epitaxial layer;
d) masked ion implantation for a charge compensation zone structure with a doping complementary to the drift zone;
e) repeating steps b) to d) until a predetermined epitaxial layer thickness is reached;
f) indiffusing of the doping materials for the drift zones and the charge compensation zones until coherent charge compensation zones are generated;
g) completing of a semiconductor chip structure for power semiconductor devices on the semiconductor wafer; and
wherein the doping with 20 to 80 atomic % of the total dopant implanted of the doping material of the first conduction type is carried out with inhomogeneous distribution during the application of the epitaxial layer in the epitaxially grown semiconductor material in such a way that a maximum of the concentration of doping material is introduced into the semiconductor material in a middle region of an individual epitaxial growth phase.

### Claim 2 (depends on 1)

The method of claim 1, wherein a doping material balance for the first conduction type, the concentration of which is higher than the concentration of the already homogeneously distributed doping material of the epitaxially grown semiconductor material, is introduced by ion implantation and diffusion.

### Claim 3 (depends on 1)

The method of claim 1, wherein a doping material balance with a concentration comprising nearly two thirds of the total concentration of doping material of the drift zones is introduced near the surface by using ion implantation and diffusion.

### Claim 4 (depends on 1)

The method of claim 1, wherein a doping material balance for drift zones is introduced over a large area and implanted without a mask into the epitaxially grown semiconductor material by ion implantation and diffusion.

### Claim 5 (depends on 1)

The method of claim 1, wherein the charge compensation zones are introduced in column- or strip-shaped regions into the epitaxially grown semiconductor material by masked ion implantation and diffusion.

### Claim 6 (depends on 1)

The method of claim 1, wherein body zones with a doping complementary to the first conduction type are introduced near the surface into the epitaxially grown semiconductor material, wherein source zones of the first conduction type with a higher doping than the drift zones are introduced into the body zones, and wherein contact holes are then produced through an insulating layer up to the source zones and the body zones, to which a conductive source electrode structure is subsequently applied.

### Claim 7 (depends on 1)

The method of claim 1, wherein the introduction of the doping materials provides a doping material dose CD in the drift zones and into the charge compensation zones which is less than the breakdown charge CL with CD≦CL of silicon with CL=2×1012 cm−2.

### Claim 8 (depends on 1)

The method of claim 1, wherein the charge compensation zones are arranged at a step size p in micrometers, with p≦11 μm.

### Claim 9 (depends on 1)

The method of claim 1, wherein, within the epitaxially grown semiconductor material, the homogeneously distributed concentration of the doping material of the drift zones never falls below zero at any time during production.

### Claim 10 (depends on 1)

The method of claim 1, wherein the completion of the semiconductor chip structures for power semiconductor devices on the semiconductor wafer is followed by the thinning of the semiconductor substrate and by its cutting into semiconductor chips.