# US 8,569,148 B2 · Final polishing method for silicon single crystal wafer and silicon single crystal wafer

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- Number: US 8,569,148 B2
- Document ID: US8569148B2
- Status: Granted
- Kind: B2
- Application number: 12/449,017
- Filed: 2008-01-29
- Published: 2010-04-15
- Granted: 2013-10-29
- Earliest claimed: 2007-02-20
- Assignees: Shin-Etsu Handotai Co., Ltd.
- Applicants: Naoto Iizuka; Hirotaka Kurimoto; Koichi Kosaka; Fumiaki Maruyama
- Inventors: Naoto Iizuka; Hirotaka Kurimoto; Koichi Kosaka; Fumiaki Maruyama
- Web page: https://patentgrep.com/patent/US8569148B2

## CPC

- B24B 37/042: {operating processes therefor}
- H10P 90/129: {by polishing}
- B24B: MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING (grinding of gear teeth B23F, of screw-threads B23G1/36; by electro-erosion B23H; abrasive or related blasting B24C; tools for grinding, buffing or sharpening B24D; polishing compositions C09G1/00; abrasives C09K3/14; electrolytic etching or polishing C25F3/00; grinding arrangements for use on assembled railway tracks E01B31/17); DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

The present invention provides a final polishing method for a silicon single crystal wafer that performs final polishing with a polishing rate being set to 10 nm/min or below at a final polishing step as a final step among a plurality of polishing steps for polishing the silicon single crystal wafer with a polishing slurry being interposed between the silicon single crystal wafer and a polishing pad, and a silicon single crystal wafer subjected to final polishing by this method. Hereby, there can be provided the final polishing method that can obtain a silicon single crystal wafer with less PIDs (Polishing Induced Defects) and the silicon single crystal wafer subjected to final polishing by this method.

## Claims

### Claim 1

A final polishing method for a silicon single crystal wafer, wherein
the method is performed before a device fabrication process, and
at a final polishing step as a final step among a plurality of polishing steps for polishing the silicon single crystal wafer with a polishing slurry being interposed between the silicon single crystal wafer and a polishing pad, the method comprising:
first setting a polishing rate to exceed 10 nm/min, and then
setting the polishing rate at least at the end of the final polishing step to 5 nm/min or below.

### Claim 2 (depends on 1)

The final polishing method for a silicon single crystal wafer according to claim 1, wherein the polishing rate in the final polishing is adjusted by adjusting a relative velocity of the silicon single crystal wafer to be polished and the polishing pad.

### Claim 3 (depends on 2)

A silicon single crystal wafer subjected to final polishing by the final polishing method for a silicon single crystal wafer according to claim 2, wherein the number of PIDs on a wafer surface is less than 100 in terms of a wafer having a diameter of 300 mm.

### Claim 4 (depends on 1)

The final polishing method for a silicon single crystal wafer according to claim 1, wherein a polishing stock removal in the final polishing is set to 5 nm or above.

### Claim 5 (depends on 4)

A silicon single crystal wafer subjected to final polishing by the final polishing method for a silicon single crystal wafer according to claim 4, wherein the number of PIDs on a wafer surface is less than 100 in terms of a wafer having a diameter of 300 mm.

### Claim 6 (depends on 2)

The final polishing method for a silicon single crystal wafer according to claim 2, wherein a polishing stock removal in the final polishing is set to 5 nm or above.

### Claim 7 (depends on 6)

A silicon single crystal wafer subjected to final polishing by the final polishing method for a silicon single crystal wafer according to claim 6, wherein the number of PIDs on a wafer surface is less than 100 in terms of a wafer having a diameter of 300 mm.

### Claim 8 (depends on 1)

A silicon single crystal wafer subjected to final polishing by the final polishing method for a silicon single crystal wafer according to claim 1, wherein the number of PIDs on a wafer surface is less than 100 in terms of a wafer having a diameter of 300 mm.

### Claim 9 (depends on 1)

The final polishing method for a silicon single crystal wafer according to claim 1, wherein a stock removal of the polishing with a polishing rate of 5 nm/min or below is 1 nm or above.