# US 8,569,144 B2 · Method of manufacturing semiconductor integrated circuit device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,569,144 B2 - Document ID: US8569144B2 - Status: Granted - Kind: B2 - Application number: 13/365,183 - Filed: 2012-02-02 - Published: 2012-05-24 - Granted: 2013-10-29 - Earliest claimed: 2009-12-01 - Assignees: Renesas Electronics Corporation - Applicants: Kota Funayama; Hiraku Chakihara - Inventors: Kota Funayama; Hiraku Chakihara - Web page: https://patentgrep.com/patent/US8569144B2 ## CPC - H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations - H10B 43/10: characterised by the top-view layout - H10B 43/40: characterised by the peripheral circuit region - H10D 30/69: IGFETs having charge trapping gate insulators, e.g. MNOS transistors - H10D 84/0133: {Manufacturing common source or drain regions between multiple IGFETs} - H10D 84/0142: {the gate conductors having different shapes or dimensions} - H10D 84/0147: {Manufacturing their gate sidewall spacers} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10W 10/0143: {comprising concurrently refilling multiple trenches having different shapes or dimensions} - G11C 16/0425: {comprising cells containing a merged floating gate and select transistor} - G11C 16/0433: {comprising cells containing a single floating gate transistor and one or more separate select transistors} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10B: ELECTRONIC MEMORY DEVICES - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract In the present invention, in the exposure to light of a memory cell array or the like of a semiconductor memory or the like, when a group of unit openings for etching the STI trench regions in which the unit openings for etching the STI trench regions each having a rectangular shape are arranged in rows and columns are transferred by the exposure onto a negative resist film, multiple exposure is appropriately used which includes a first exposure step using a first optical mask having a group of first linear openings extending in a column direction and a second exposure step using a second optical mask having a group of second linear openings extending in a row direction. ## Claims ### Claim 1 A method of manufacturing a semiconductor integrated circuit device, comprising the steps of: (a) forming a silicon-nitride-based film over a first main surface of a wafer; (b) forming a silicon-oxide-based film over the silicon-nitride-based film; (c) processing the silicon-oxide-based film and a resist film disposed over the silicon-oxide-based film using a lithography process to form a group of first linear films extending in a column direction and openings such that the silicon-nitride-based film remains under the group of first linear films and the openings; (d) after the step (c), forming a resist film over the first main surface, and exposing the resist film to light; (e) subjecting the resist film to a development process to form a group of second linear films extending in a row direction; (f) after the step (e), in a state where there are the group of first linear films and the group of second linear films, performing an etching process to the first main surface to form, in a portion of the first main surface serving as a memory cell array, a plurality of STI unit trench regions each having a rectangular shape longer in the row direction than in the column direction into a matrix arranged in the column direction and the row direction; (g) forming a STI buried insulating film over the first main surface so as to be buried in the STI unit trench regions; (h) subjecting the STI buried insulating film located outside the STI unit trench regions to a planarization process to form a group of STI regions arranged in a matrix; and (i) after the step (h), forming first and second word lines longitudinally traversing, at predetermined space intervals, each row of the group of STI regions arranged in the matrix by a lithography process, wherein alignment in an exposure step in the lithography process in the step (i) is performed using positions in the column direction of the group of STI regions arranged in the matrix as a reference. ### Claim 2 (depends on 1) A method of manufacturing a semiconductor integrated circuit device according to claim 1, further comprising the step of: (j) after the step (i), forming first and second electrode lines along and outside respective first and second word lines by self-alignment. ### Claim 3 (depends on 1) A method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the planarization process includes a chemical mechanical polishing step. ### Claim 4 (depends on 1) A method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the memory cell array is a cell array of a NOR-type flash memory. ### Claim 5 (depends on 2) A method of manufacturing a semiconductor integrated circuit device according to claim 2, wherein the memory cell array is a cell array of a split-gate flash memory having a charge accumulation film. ### Claim 6 A method of manufacturing a semiconductor integrated circuit device, comprising the steps of: (a) forming a silicon-nitride-based film over a first main surface of a wafer; (b) forming a silicon-oxide-based film over the silicon-nitride-based film; (c) processing the silicon-oxide-based film by a lithography process to form a group of first linear films extending in a first direction and openings such that the silicon-nitride-based film remains under the group of first linear films and the openings; (d) after the step (c), forming a resist film over the first main surface, and exposing the resist film to light; (e) subjecting the resist film to a development process to form a group of second linear films extending in a second direction perpendicular to the first direction; (f) after the step (e), in a state in which the group of first linear films and the group of second linear films have been formed, performing an etching process to the first main surface to form, in a portion of the first main surface serving as a memory cell array, a plurality of STI unit trench regions each having a rectangular shape longer in the first direction than in the second direction and formed into a matrix arranged in the first direction and the second direction; (g) forming a STI buried insulating film over the first main surface so as to be buried in the STI unit trench regions; (h) subjecting the STI buried insulating film located outside the STI unit trench regions to a planarization process to form a group of STI regions arranged in a matrix; and (i) after the step (h), forming first and second word lines longitudinally traversing, at predetermined space intervals, each row of the group of STI regions arranged in the matrix by a lithography process, wherein alignment in an exposure step in the lithography process in the step (i) is performed using positions in the second direction of the group of STI regions arranged in the matrix as a reference. ### Claim 7 (depends on 6) A method of manufacturing a semiconductor integrated circuit device according to claim 6, further comprising the step of: (j) after the step (i), forming first and second electrode lines along and outside respective first and second word lines by self-alignment. ### Claim 8 (depends on 6) A method of manufacturing a semiconductor integrated circuit device according to claim 6, wherein the planarization process includes a chemical mechanical polishing step. ### Claim 9 (depends on 6) A method of manufacturing a semiconductor integrated circuit device according to claim 6, wherein the memory cell array is a cell array of a NOR-type flash memory. ### Claim 10 (depends on 7) A method of manufacturing a semiconductor integrated circuit device according to claim 7, wherein the memory cell array is a cell array of a split-gate flash memory having a charge accumulation film. ### Claim 11 A method of manufacturing a semiconductor integrated circuit device including memory cells, comprising the steps of: (a) forming a first film over a semiconductor substrate; (b) forming a second film over the silicon-nitride-based film; (c) patterning the first film by a lithography process to form a group of first patterns extending in a first direction and openings formed between the first patterns such that the second film remains under the group of first patterns and the openings; (d) after the step (c), forming a resist film over the semiconductor substrate, and exposing the resist film to light; (e) forming the resist film to a development process to form a group of second patterns extending in a second direction perpendicular to the first direction; (f) after the step (e), in a state in which the group of first patterns and the group of second patterns have been formed, performing an etching process to form, in a portion of the semiconductor substrate serving as a memory cell array, a plurality of STI unit trench regions each having a rectangular shape and formed into a matrix arranged in the first direction and the second direction; (g) burying an insulating film in the STI unit trench regions; (h) forming a group of STI regions arranged in a matrix by removing the insulating film located outside the STI unit trench regions; and (i) after the step (h), forming word lines extending in the first direction and longitudinally traversing each row of the group of STI regions by a lithography process, wherein alignment in an exposure step in the lithography process in the step (i) is performed using positions in the first direction of the group of STI regions as a reference. ### Claim 12 (depends on 11) A method of manufacturing a semiconductor integrated circuit device according to claim 11, further comprising the step of: (j) after the step (i),forming first and second electrode lines along and outside respective word lines by self-alignment. ### Claim 13 (depends on 11) A method of manufacturing a semiconductor integrated circuit device according to claim 11, wherein the planarization process includes a chemical mechanical polishing step. ### Claim 14 (depends on 11) A method of manufacturing a semiconductor integrated circuit device according to claim 11, wherein the memory cell array is a cell array of a NOR-type flash memory. ### Claim 15 (depends on 12) A method of manufacturing a semiconductor integrated circuit device according to claim 12, wherein the memory cell array is a cell array of a split-gate flash memory having a charge accumulation film.