# US 8,569,142 B2 · Multi-level thin film capacitor on a ceramic substrate and method of manufacturing the same

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- Number: US 8,569,142 B2
- Document ID: US8569142B2
- Status: Granted
- Kind: B2
- Application number: 11/736,408
- Filed: 2007-04-17
- Published: 2007-09-13
- Granted: 2013-10-29
- Earliest claimed: 2003-11-28
- Assignees: BlackBerry Limited
- Applicants: Ivoyl P. Koutsaroff; Mark Vandermeulen; Andrew Cervin-Lawry; Atin J. Patel
- Inventors: Ivoyl P. Koutsaroff; Mark Vandermeulen; Andrew Cervin-Lawry; Atin J. Patel
- Web page: https://patentgrep.com/patent/US8569142B2

## CPC

- H01G 4/38: Multiple capacitors, i.e. structural combinations of fixed capacitors
- H01G 4/33: Thin- or thick-film capacitors {(thin- or thick-film circuits; capacitors without a potential-jump or surface barrier specially adapted for integrated circuits, details thereof, multistep manufacturing processes therefor)}
- H01G 13/04: Drying; Impregnating
- H05K 1/162: {incorporating printed capacitors}
- H10D 86/85: characterised by only passive components
- H05K 1/0306: {Inorganic insulating substrates, e.g. ceramic, glass}
- H05K 3/38: Improvement of the adhesion between the insulating substrate and the metal
- H05K 3/388: {by the use of a metallic or inorganic thin film adhesion layer}
- H05K 2201/0175: Inorganic, non-metallic layer, e.g. resist or dielectric for printed capacitor
- H05K 2201/0179: Thin film deposited insulating layer, e.g. inorganic layer for printed capacitor
- Y10T 29/49126: Assembling bases
- Y10T 29/49155: Manufacturing circuit on or in base
- H01G: CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE (selection of specified materials as dielectric H01B3/00; capacitors having potential barriers H10D1/62, H10K10/10)
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- Y10T: TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION

## Abstract

In accordance with the teachings described herein, a multi-level thin film capacitor on a ceramic substrate and method of manufacturing the same are provided. The multi-level thin film capacitor (MLC) may include at least one high permittivity dielectric layer between at least two electrode layers, the electrode layers being formed from a conductive thin film material. A buffer layer may be included between the ceramic substrate and the thin film MLC. The buffer layer may have a smooth surface with a surface roughness (Ra) less than or equal to 0.08 micrometers (um).

## Claims

### Claim 1

A method of manufacturing a thin film integrated circuit, comprising:
obtaining a ceramic substrate;
depositing a glass dielectric buffer layer over the substrate;
smoothing the buffer layer's surface to a surface roughness (Ra) of less than or equal to 0.08 microns and substantially free of surface micropores;
forming multiple layers of a thin film multi-level capacitor over the buffer layer surface, the forming of the multiple capacitor layers including providing high permittivity dielectric layers interleaved between electrode layers to form multiple capacitors stacked on each other, wherein pairs of the multiple capacitors share a common electrode therebetween, and wherein a bottom electrode of a bottom capacitor of the multiple capacitors is formed directly on the buffer layer;
annealing each capacitor layer before forming the successive capacitor layer;
forming a high density interconnect layer between the ceramic substrate and the buffer layer, wherein the deposited buffer layer provides electrical isolation between the high density interconnect layer and the thin film multi-level capacitor; and
forming a contact via through the buffer layer and the high density interconnect layer to provide electrical contact for the thin film multi-level capacitor.

### Claim 2 (depends on 1)

The method of claim 1, comprising performing a heat treatment after each electrode layer of the multi-level capacitor is formed, wherein the multiple capacitors are formed in a mesa structure, and wherein the multiple layers of the thin film multi-level capacitor are each single layers of a barium strontium titanium oxide dielectric material.

### Claim 3 (depends on 1)

The method of claim 1, comprising performing a heat treatment after each electrode layer of the multi-level capacitor is formed, wherein the surface roughness (Ra) of the buffer layer is less than or equal to 0.06 micrometers (um) and wherein the multiple layers of the thin film multi-level capacitor are each single layers of a barium strontium titanium oxide dielectric material.

### Claim 4 (depends on 1)

The method of claim 1, further comprising:
depositing one or more high permittivity dielectric layer and one or more additional thin film electrode layers over the second thin film electrode layer to form additional capacitors in the capacitor.

### Claim 5 (depends on 1)

The method of claim 1, further comprising:
depositing an interlayer dielectric layer over the buffer layer and the capacitor;
fabricating one or more additional passive thin film devices on the interlayer dielectric layer; and
depositing an interconnect layer to electrically couple the one or more additional passive thin film devices to the thin-film multi-level capacitor.

### Claim 6 (depends on 1)

The method of claim 1, wherein the high permittivity dielectric layer is a compound containing Barium Strontium Titanium Oxide, forming a tunable capacitor, and wherein a first capacitor of the multiple capacitors has different capacitance-voltage characteristics than a second capacitor of the multiple capacitors.

### Claim 7 (depends on 1)

The method of claim 1, wherein the ceramic substrate includes a layer of Al2O3.

### Claim 8 (depends on 1)

The method of claim 1, wherein the ceramic substrate includes a layer of one of AlN, Mg2SiO4 or MgTiO3.

### Claim 9 (depends on 1)

The method of claim 1, wherein a first capacitor of the multiple capacitors is a voltage tunable capacitor and wherein a second capacitor of the multiple capacitors is a fixed value capacitor.

### Claim 10 (depends on 9)

The method of claim 9, wherein the multiple capacitors are in a mesa structure.

### Claim 11 (depends on 1)

The method of claim 1, wherein the thin film multi-level capacitor has an overall capacitance density of about 10 fF/um2 to about 390 fF/um2.

### Claim 12 (depends on 1)

The method of claim 1, wherein the step of depositing a buffer layer comprises: depositing one or more layers of thick film material over the ceramic based substrate; and polishing a top surface of the thick film material to create the smooth surface.

### Claim 13

A method of manufacturing a thin film integrated circuit, comprising:
obtaining a ceramic substrate;
depositing a glass dielectric buffer layer over the substrate;
smoothing the buffer layer's surface;
forming multiple layers of a thin film multi-level capacitor over the buffer layer surface, the forming of the multiple capacitor layers including providing high permittivity dielectric layers interleaved between electrode layers to form multiple capacitors stacked on each other, wherein pairs of the multiple capacitors share a common electrode therebetween;
annealing each capacitor layer before forming the successive capacitor layer; and
forming a high density interconnect layer between the ceramic substrate and the buffer layer, wherein the deposited buffer layer provides electrical isolation between the high density interconnect layer and the thin film multi-level capacitor.

### Claim 14 (depends on 13)

The method of claim 13, comprising:
forming a contact via through the buffer layer and the high density interconnect layer to provide electrical contact between the thin film multi-level capacitor and a bonding pad formed on an underside of the substrate; and
performing a heat treatment after each electrode layer of the multi-level capacitor is formed, wherein the buffer layer surface is smoothed to a Ra roughness of less than or equal to 0.08 microns, wherein a bottom electrode of a bottom capacitor of the multiple capacitors is formed directly on the buffer layer, and wherein the multiple layers of the thin film multi-level capacitor are each single layers of a dielectric material.

### Claim 15

A method of manufacturing a thin film integrated circuit, comprising:
obtaining a ceramic substrate;
depositing a glass dielectric buffer layer over the substrate;
smoothing the buffer layer's surface;
forming multiple layers of a thin film multi-level capacitor over the buffer layer surface, the forming of the multiple capacitor layers including providing high permittivity dielectric layers directly interleaved between electrode layers to form multiple capacitors stacked on each other, wherein pairs of the multiple capacitors share a common electrode therebetween, wherein at least a first capacitor of the multiple capacitors is a tunable capacitor; and
forming a high density interconnect layer between the ceramic substrate and the buffer layer, wherein the deposited buffer layer provides electrical isolation between the high density interconnect layer and the thin-film multi-level capacitor.

### Claim 16 (depends on 15)

The method of claim 15, comprising:
forming a contact via through the buffer layer and the high density interconnect layer to provide electrical contact between the thin film multi-level capacitor and a bonding pad formed on an underside of the substrate; and
performing a heat treatment after each electrode layer of the multi-level capacitor is formed, wherein the buffer layer surface is smoothed to a Ra roughness of less than or equal to 0.08 microns, wherein the multiple layers of the thin film multi-level capacitor are each single layers of a dielectric material.

### Claim 17 (depends on 16)

The method of claim 16, further comprising forming the high density interconnect layer from one of tungsten or molybdenum, wherein the dielectric material comprises barium strontium titanium oxide.

### Claim 18 (depends on 15)

The method of claim 15, comprising forming a protective coating on an underside of the substrate, wherein the multiple capacitors are formed in a mesa structure.

### Claim 19 (depends on 15)

The method of claim 15, further comprising forming an adhesion layer between the buffer layer surface and the thin film multi-level capacitor, wherein a bottom electrode of a bottom capacitor of the multiple capacitors is formed directly on the buffer layer.

### Claim 20 (depends on 15)

The method of claim 15, wherein the multiple capacitors have an overall capacitance density of about 10 fF/um2 to about 390 fF/um2, and wherein a first capacitor of the multiple capacitors has different capacitance-voltage characteristics than a second capacitor of the multiple capacitors.