# US 8,569,140 B2 · Method of fabricating semiconductor device

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- Number: US 8,569,140 B2
- Document ID: US8569140B2
- Status: Granted
- Kind: B2
- Application number: 13/194,030
- Filed: 2011-07-29
- Published: 2012-03-01
- Granted: 2013-10-29
- Earliest claimed: 2010-08-27
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Kyu-Tae Kim; Jong-Seo Hong; Tae-Han Kim
- Inventors: Kyu-Tae Kim; Jong-Seo Hong; Tae-Han Kim
- Web page: https://patentgrep.com/patent/US8569140B2

## CPC

- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 30/0275: {forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions}
- H10D 30/608: {having non-planar bodies, e.g. having recessed gate electrodes}
- H10D 64/01324: {characterised by the sectional shape, e.g. T or inverted-T}
- H10D 64/01352: {with sacrificial oxide}
- H10D 64/018: {Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method for fabricating a semiconductor device is disclosed. One embodiment of the method includes forming a dummy gate pattern on a substrate, forming an interlayer dielectric film that covers the dummy gate pattern, exposing a top surface of the dummy gate pattern, selectively removing the dummy gate pattern to form a first gate trench, forming a sacrificial layer pattern over a top surface of the substrate in the first gate trench, the sacrificial layer pattern leaving a top portion of the first gate trench exposed, increasing an upper width of the exposed top portion of the first gate trench to form a second gate trench, and removing the sacrificial layer pattern in the second gate trench, and forming a non-dummy gate pattern in the second gate trench.

## Claims

### Claim 1

A method of fabricating a semiconductor device comprising:
forming a dummy gate pattern on a substrate;
forming an interlayer dielectric film that covers the dummy gate pattern;
exposing a top surface of the dummy gate pattern;
selectively removing the dummy gate pattern to form a first gate trench;
forming a sacrificial layer pattern over a top surface of the substrate in the first gate trench, the sacrificial layer pattern leaving a top portion of the first gate trench exposed;
increasing an upper width of the exposed top portion of the first gate trench to form a second gate trench;
removing the sacrificial layer pattern in the second gate trench;
after removing the sacrificial layer pattern in the second gate trench, forming a gate insulation layer in the second gate trench; and
forming a non-dummy gate pattern in the second gate trench.

### Claim 2 (depends on 1)

The method of claim 1, wherein at least a portion of the non-dummy gate pattern includes a metal, and
wherein the forming a non-dummy gate pattern comprises:
forming a metal film on the substrate and the interlayer dielectric layer, the metal film filling the second gate trench;
removing the metal film on the interlayer dielectric film; and
reducing a height of the second gate trench.

### Claim 3 (depends on 1)

The method of claim 1, wherein a width of a topmost portion of the second gate trench is greater than a width of a bottommost portion of the second gate trench.

### Claim 4 (depends on 1)

The method of claim 1, wherein
prior to forming the non-dummy gate pattern, a sidewall defined by the second gate trench has (1) a vertical profile from the bottommost portion of the second gate trench to a first height in the second grate trench and (2) an upwardly sloping profile in which the width of the second gate trench increases from the first height to a topmost portion of the second gate trench.

### Claim 5 (depends on 1)

The method of claim 1, wherein a top surface of the sacrificial layer pattern is lower than a top surface of the interlayer dielectric film.

### Claim 6 (depends on 5)

The method of claim 5, wherein the sacrificial layer pattern includes at least one of an organic layer and an oxide layer.

### Claim 7 (depends on 6)

The method of claim 6, wherein the organic layer includes a spin on hard mask (SOH).

### Claim 8 (depends on 6)

The method of claim 6, wherein the oxide layer includes a layer selected from the group consisting of tonen silazene (TOSZ) layer, a spin on glass (SOG) layer, a flowable-chemical vapor deposition (F-CVD) layer, or an undoped silica glass (USG) layer.

### Claim 9 (depends on 6)

The method of claim 6, wherein the forming the sacrificial layer pattern comprises:
forming a sacrificial layer that fills the first gate trench and covers the substrate; and
removing a portion of the sacrificial layer in the first gate trench.

### Claim 10 (depends on 1)

The method of claim 1, wherein before the forming the interlayer dielectric film that covers the dummy gate pattern, the method further comprises:
forming a spacer on sidewalls defined by the dummy gate pattern; and
forming an elevated epitaxial layer above the substrate.

### Claim 11 (depends on 10)

The method of claim 10, further comprising:
forming source/drain regions in the elevated epitaxial layer and the substrate.

### Claim 12 (depends on 1)

The method of claim 1, wherein before the forming the interlayer dielectric film that covers the dummy gate pattern, the method further comprises:
forming an etch stopper film (1) over the substrate and (2) over the dummy gate pattern.

### Claim 13

A method of fabricating a semiconductor device, the method comprising:
forming a dummy gate pattern on a substrate;
forming an interlayer dielectric film that covers the dummy gate pattern;
forming a first gate forming trench in the interlayer dielectric film by selectively removing the dummy gate pattern, the first gate trench defining inner walls;
forming a sacrificial layer pattern on a top surface of the substrate in the first gate trench while exposing a top portion of the first gate trench, the sacrificial layer pattern does not contact a portion of the inner walls of the first gate trench;
forming a second gate trench by etching the portion of the inner wall of the first gate trench that does not contact the sacrificial layer pattern, the second gate trench (1) having a topmost width greater than a bottommost width and (2) defining an inner wall that includes (i) a portion not in contact with the sacrificial layer pattern and (ii) a portion in contact with the sacrificial layer pattern;
removing the sacrificial layer pattern in the second gate trench; and
forming a non-dummy gate pattern in the second gate trench.

### Claim 14 (depends on 13)

The method of claim 13, wherein before the removing the sacrificial layer pattern, the inner wall portion of the second gate trench not in contact with the sacrificial layer pattern has a sloping profile in which the width of the second gate trench increases upwardly.

### Claim 15 (depends on 14)

The method of claim 14, wherein before the removing the sacrificial layer pattern, the inner wall portion of the second gate trench in contact with the sacrificial layer pattern has a vertical profile.

### Claim 16

A method of fabricating a semiconductor device, the method comprising:
forming a dielectric layer above a substrate;
forming a first gate trench in the dielectric layer, the first gate trench having sidewalls;
forming a sacrificial pattern layer in the first gate trench, the sacrificial pattern layer having an upper surface that is below an upper surface of the dielectric layer;
after forming the sacrificial pattern layer in the first gate trench, increasing a width of at least a portion of the first gate trench to form a second gate trench such that a width of at least a portion of second gate trench decreases from the upper surface of the dielectric layer;
removing the sacrificial pattern layer;
after removing the sacrificial pattern layer, forming a gate insulation layer in the second gate trench; and
forming a first gate metal film in the second gate trench.

### Claim 17 (depends on 16)

The method of claim 16, wherein the forming the dielectric layer above the substrate comprises:
forming a dummy gate pattern layer over the substrate;
forming a spacer layer over sidewalls defined by the dummy gate pattern layer; and
forming an interlayer dielectric layer above the spacer layer.

### Claim 18 (depends on 17)

The method of claim 17, wherein the increasing the width of at least the portion of the first gate trench to form the second gate trench is performed by a wet etching or a dry etching process that removes portions of the spacer layer.

### Claim 19 (depends on 16)

The method of claim 16, wherein a sidewall defining the second gate trench has a tapered profile from the upper surface of the dielectric layer to a first height in the second gate trench, and has a vertical profile below the first height.