Method of improving PMOS performance in a contact etch stop layer process

Abstract

A method of improving PMOS performance in a contact etch stop layer process is disclosed. The method includes: a first step for sequentially forming a first silicon dioxide layer, a hydrogen-containing silicon nitride layer and a second silicon dioxide layer on a semiconductor wafer; a second step for etching the second silicon dioxide layer; a third step for irradiating the resulting structure obtained after the step 2 with ultra-violet light; and a fourth step for removing the portions of the second silicon dioxide layer remained over the PMOS devices. By irradiating the low-stress silicon nitride layer deposited over the NMOS devices by UV light, a high tensile stress is generated in the silicon nitride over the NMOS devices while there is no high tensile stress in the silicon nitride over the PMOS devices, thus reducing disadvantageous effects of the CESL process on the performance of PMOS devices.

Dependencies are inferred from the claim text.