# US 8,569,132 B2 · Semiconductor device and manufacturing method thereof

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- Number: US 8,569,132 B2
- Document ID: US8569132B2
- Status: Granted
- Kind: B2
- Application number: 13/361,010
- Filed: 2012-01-30
- Published: 2012-08-02
- Granted: 2013-10-29
- Earliest claimed: 2011-01-31
- Assignees: Renesas Electronics Corporation
- Applicants: Nobuo Machida; Koichi Arai
- Inventors: Nobuo Machida; Koichi Arai
- Web page: https://patentgrep.com/patent/US8569132B2

## CPC

- H10D 30/66: Vertical DMOS [VDMOS] FETs
- H10D 12/031: {of IGBTs}
- H10D 30/0291: {of vertical DMOS [VDMOS] FETs}
- H10D 62/8325: {Silicon carbide}
- H10D 62/117: {Shapes of semiconductor bodies}
- H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs}
- H10D 62/405: {Orientations of crystalline planes}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

In a SiC-based MISFET and a manufacturing process thereof, after the introduction of an impurity, extremely-high-temperature activation annealing is required. Accordingly, it is difficult to frequently use a self-alignment process as performed in a silicon-based MISFET manufacturing process. This results in the problem that, to control the characteristics of a device, a high-accuracy alignment technique is indispensable. In accordance with the present invention, in a semiconductor device such as a SiC-based vertical power MISFET using a silicon-carbide-based semiconductor substrate and a manufacturing method thereof, a channel region, a source region, and a gate structure are formed in mutually self-aligned relation.

## Claims

### Claim 1

A method of manufacturing a semiconductor device, comprising the steps of:
(a) preparing a semiconductor wafer having, in a first main surface of a silicon-carbide-based semiconductor substrate having a first conductivity type, a first silicon-carbide-based semiconductor layer having the same conductivity type as the first conductivity type and a concentration lower than that of the semiconductor substrate;
(b) introducing, into a surface region of the first silicon-carbide-based semiconductor layer closer to the first main surface, a second-conductivity-type region having a second conductivity type opposite to the first conductivity type and serving as a channel region of a vertical power MISFET;
(c) introducing a source region of the vertical power MISFET having the same conductivity type as the first conductivity type and a concentration higher than that of the first silicon-carbide-based semiconductor layer in self-aligned relation with the second-conductivity-type region;
(d) after step (c), performing an activation anneal treatment for the second-conductivity-type region and the source region; and
(e) after step (d), forming a gate structure of the vertical power MISFET in self-aligned relation with the source region,
wherein the first silicon-carbide-based semiconductor layer is an epitaxial layer,
wherein self-alignment of the source region with the second-conductivity-type region is performed using sidewalls each formed of a silicon-based insulating film, and
wherein self-alignment of the gate structure with the source region is performed using an opening pattern of a carbon film.

### Claim 2 (depends on 1)

A method of manufacturing a semiconductor device according to claim 1,
wherein a gate insulating film forming the gate structure is a thermal oxide film.

### Claim 3 (depends on 1)

A method of manufacturing a semiconductor device according to claim 1,
wherein a gate insulating film forming the gate structure is an insulating film deposited by CVD.

### Claim 4 (depends on 3)

A method of manufacturing a semiconductor device according to claim 3,
wherein the CVD is ALD.

### Claim 5 (depends on 4)

A method of manufacturing a semiconductor device according to claim 4,
wherein the gate insulating film forming the gate structure has an alumina-based insulating film.

### Claim 6 (depends on 5)

A method of manufacturing a semiconductor device according to claim 5, further comprising the step of:
(f) after the step (e) and prior to the step (d), enlarging the opening pattern of the carbon film by a dimension substantially equal to a thickness of the gate insulating film.

### Claim 7 (depends on 1)

A method of manufacturing a semiconductor device according to claim 1,
wherein the first main surface of the semiconductor substrate is a (0001) plane or a plane equivalent thereto.