# US 8,569,131 B2 · Source/drain-to-source/drain recessed strap and methods of manufacture of same

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- Number: US 8,569,131 B2
- Document ID: US8569131B2
- Status: Granted
- Kind: B2
- Application number: 12/949,888
- Filed: 2010-11-19
- Published: 2012-05-24
- Granted: 2013-10-29
- Earliest claimed: 2010-11-19
- Assignees: International Business Machines Corporation
- Applicants: Brent A. Anderson; Edward J. Nowak; Jed H. Rankin
- Inventors: Brent A. Anderson; Edward J. Nowak; Jed H. Rankin
- Web page: https://patentgrep.com/patent/US8569131B2

## CPC

- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A structure and a method of making the structure. The structure includes first and second semiconductor regions in a semiconductor substrate and separated by a region of trench isolation in the semiconductor substrate; a first gate electrode extending over the first semiconductor region; a second gate electrode extending over the second semiconductor region; a trench contained in the region of trench isolation and between and abutting the first and second semiconductor regions; and an electrically conductive strap in the trench, the strap electrically connecting the first and second semiconductor regions.

## Claims

### Claim 1

A method, comprising:
forming trench isolation in a semiconductor substrate, said trench isolation separating first and second semiconductor regions in said semiconductor substrate;
forming a trench in a region of said trench isolation and between and abutting said first and second semiconductor regions; and
simultaneously forming a first gate electrode extending over said first semiconductor region, a second gate electrode extending over said second semiconductor region, and an electrically conductive strap in said trench, said strap physically abutting and electrically connecting said first and second semiconductor regions.

### Claim 2 (depends on 1)

The method of claim 1, wherein said first and second gate electrodes and said strap are unconnected regions of a same layer of a same material.

### Claim 3 (depends on 1)

The method of claim 1, wherein a top surface of said strap is recessed below a top surface of said trench isolation and respective top surfaces of said first and second semiconductor regions.

### Claim 4 (depends on 1)

The method of claim 1, wherein said first and second gate electrodes and said strap comprise polysilicon.

### Claim 5 (depends on 1)

The method of claim 1, further including:
forming a metal silicide layer on top surfaces of said first and second gate electrodes and said strap.

### Claim 6 (depends on 1)

The method of claim 1, further including:
forming a first gate dielectric layer between said first gate electrode and said first semiconductor region and a second gate dielectric layer between said second gate electrode and said second semiconductor region; and
forming first source/drains in said first region on opposite sides of first gate electrode and second source/drains in said second region on opposite sides of second gate electrode.

### Claim 7 (depends on 6)

The method of claim 6, wherein said strap electrically connects a source/drain of said first source/drains to a source/drain of said second source/drains.

### Claim 8 (depends on 1)

The method of claim 1, wherein:
first major axes of said first and second gate electrodes and said strap are parallel in a first direction that is parallel to a top surface of said semiconductor substrate;
second major axes of said first and second semiconductor regions are parallel in a second direction that is parallel to said top surface of said semiconductor substrate; and
wherein said first and second directions are perpendicular.

### Claim 9 (depends on 1)

The method of claim 1, further including:
simultaneously forming a first trench in said first semiconductor region and a second trench in said second semiconductor region, said trench between and opening into said first and second trenches.

### Claim 10 (depends on 9)

The method of claim 9, wherein a depth of said first and second trenches measured in a direction perpendicular to a top surface of said substrate are different from a depth of said third trench measured in said direction perpendicular to a top surface of said substrate.

### Claim 11 (depends on 1)

The method of claim 1, wherein said trench isolation is dielectric isolation.

### Claim 12 (depends on 1)

The method of claim 1, wherein said trench isolation is formed from a dielectric material, said dielectric material extending from said first semiconductor region to said second semiconductor region.

### Claim 13 (depends on 1)

The method of claim 1, wherein said strap physically and electrically only contacts sidewalls of said first and second semiconductor regions.

### Claim 14 (depends on 1)

The method of claim 1, including:
simultaneously forming a first metal silicide layer on top surface said first gate electrode, a second metal silicide layer on top surface said second gate electrode, and on a top surface of said strap.

### Claim 15 (depends on 1)

The method of claim 1, wherein said strap extends into said first semiconductor region and said second semiconductor region.

### Claim 16 (depends on 1)

The method of claim 1, wherein said trench does not extend through said trench isolation in a direction perpendicular to a top surface of said semiconductor substrate.

### Claim 17 (depends on 1)

The method of claim 1, wherein said trench is formed in said trench isolation and in a first region of said first semiconductor region and in second region of said first semiconductor region.

### Claim 18 (depends on 17)

The method of claim 17, wherein said trench does not extend through said trench isolation in a direction perpendicular to a top surface of said semiconductor substrate.

### Claim 19 (depends on 1)

The method of claim 1, including:
after forming said first and second gate electrodes and said strap, ion implanting a dopant species into said strap and said first and second semiconductor regions where said semiconductor regions are not covered by said first and second gate electrodes.

### Claim 20 (depends on 1)

The method of claim 1, including:
(a) etching said trench into said trench isolation;
after (a), (b) forming a polysilicon layer on top surfaces of said first and second semiconductor regions and said trench isolation, said polysilicon layer filling said trench;
after (b), (c) removing selected regions of said polysilicon layer to form said first and second gate electrodes and said strap;
after (c), (d) forming source/drains in said first and second semiconductor regions where said semiconductor regions are not protected by said first and second source/drains.