# US 8,569,128 B2 · Semiconductor structure and method of fabrication thereof with mixed metal types

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- Number: US 8,569,128 B2
- Document ID: US8569128B2
- Status: Granted
- Kind: B2
- Application number: 12/960,266
- Filed: 2010-12-03
- Published: 2011-12-22
- Granted: 2013-10-29
- Earliest claimed: 2010-06-21
- Assignees: SuVolta, Inc.
- Applicants: Lucian Shifren; Pushkar Ranade; Sachin R. Sonkusale
- Inventors: Lucian Shifren; Pushkar Ranade; Sachin R. Sonkusale
- Web page: https://patentgrep.com/patent/US8569128B2

## CPC

- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 62/314: {having vertical doping variations (vertical IGFETs H10D30/63)}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/0177: {the gate conductors having different materials or different implants}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/856: {the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor structure includes a first PMOS transistor element having a gate region with a first gate metal associated with a PMOS work function and a first NMOS transistor element having a gate region with a second metal associated with a NMOS work function. The first PMOS transistor element and the first NMOS transistor element form a first CMOS device. The semiconductor structure also includes a second PMOS transistor that is formed in part by concurrent deposition with the first NMOS transistor element of the second metal associated with a NMOS work function to form a second CMOS device with different operating characteristics than the first CMOS device.

## Claims

### Claim 1

A method for forming a semiconductor structure, comprising;
forming first and second PMOS transistor elements and first and second NMOS transistor elements, wherein the first PMOS transistor element and the first NMOS transistor element establish a first CMOS transistor pair, and the second PMOS transistor element and the second NMOS transistor element establish a second CMOS transistor pair, by:
forming a first threshold voltage setting region extending under a gate of the first and second PMOS transistor elements, the first threshold voltage region defining a depletion zone when a voltage to the transistor elements is applied;
forming a second threshold voltage setting region extending under a gate of the first and second NMOS transistor elements, the second threshold voltage region defining a depletion zone when the voltage to the transistor elements is applied;
forming a substantially undoped channel region, disposed above the threshold voltage setting regions and below the gates of each of the first and second PMOS and NMOS transistor elements;
concurrently depositing a first gate metal only on the gate of the first PMOS transistor element of the first CMOS transistor pair and the gate of the second NMOS transistor element of the second CMOS transistor pair; and
concurrently depositing a second gate metal only on the gate of the first NMOS transistor element of the first CMOS transistor pair and the gate of the second PMOS transistor element of the second CMOS transistor pair.

### Claim 2 (depends on 1)

The method of claim 1, wherein the second gate metal is a modification of the first gate metal.

### Claim 3 (depends on 1)

The method of claim 1, wherein at least one of the first gate metal and the second gate metal has a work function between 100 millivolts from band edge to midgap.

### Claim 4 (depends on 1)

The method of claim 1, wherein at least one of the first gate metal and the second gate metal has a work function selected to be between midgap and 300 millivolts from midgap.

### Claim 5 (depends on 1)

The method of claim 1, further comprising:
forming the gates of the first and second PMOS transistor elements and the first and second NMOS transistor elements after forming respective source and drain regions.

### Claim 6 (depends on 1)

The method of claim 1, further comprising:
forming the gates of the first and second PMOS transistor elements and the first and second NMOS transistor elements prior to forming respective source and drain regions.

### Claim 7 (depends on 1)

The method, of claim 1, further comprising:
forming a body tap region for at least one of the first and second PMOS transistor elements and first and second NMOS transistor elements to selectively apply a bias thereto.

### Claim 8 (depends on 1)

The method of claim 1, wherein the undoped channel is formed by epitaxial growth of silicon.

### Claim 9 (depends on 1)

The method of claim 1, wherein the first NMOS transistor element is formed to operate with a predetermined first leakage, the second NMOS transistor element being formed to operate with a second leakage at least ten times lower than the predetermined first leakage.

### Claim 10 (depends on 1)

The method of claim 1, wherein the first NMOS transistor element is formed to operate with a predetermined first leakage, the second NMOS transistor element being formed to operate with a second leakage at least fifty times lower than the predetermined first leakage.