US 8,569,126 B2Granted

Semiconductor device and manufacturing method thereof

AssigneeFujitsu Semiconductor Limited

InventorYoshihiro Takao

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Abstract

A semiconductor device includes a silicon substrate in which active regions of a memory cell are defined, a gate electrode formed on a device isolation insulating film to extend in a first direction, a first insulating film formed on the silicon substrate and the gate electrode, a first plug formed to penetrate the first insulating film, to overlap with the gate electrode and the first active region, and to extend in a second direction perpendicular to the first direction, a second plug penetrating the first insulating film above the second active region, a second insulating film formed on the first insulating film, and an interconnection buried in the second insulating film, and formed to recede from a side surface of the first plug in the second direction and to cover only part of an upper surface of the first plug.

Claims12

Dependent claims

A method of manufacturing a semiconductor device comprising:

defining, in a semiconductor substrate, a first active region and a second active region by forming a device isolation insulating film over the semiconductor substrate;
forming a gate electrode, extending in a first direction, over the device isolation insulating film and the first active region;
forming a first insulating film over the semiconductor substrate and the gate electrode;
forming a second insulating film over the first insulating film;
forming a first hole, a second hole and a third hole by patterning the first insulating film and the second insulating film, the first hole having a rectangular planar shape overlapping with the gate electrode and the first active region and extending in a second direction perpendicular to the first direction, the second hole being located over the second active region;
forming a trench by patterning the second insulating film, the trench extending from a position over the first hole to a position over the second hole;
and
forming first, second, and third plugs in the first, second, and third holes and forming an interconnection in the trench, thereby forming the interconnection integrally formed with the first plug and the second plug.

5 more elements

A method of manufacturing a semiconductor device comprising:

defining, in a semiconductor substrate, a first active region and a second active region by forming a device isolation insulating film in the semiconductor substrate;
defining, in a semiconductor substrate, a third active region and a fourth active region between the first active region and the second active region, by forming the device isolation insulating film in the semiconductor substrate;
implanting a p-type ion in the first active region and the second active region;
implanting a n-type ion in the third active region and the fourth active region;
forming a first gate electrode over the first active region, the third active region and the device isolation insulating film, extending in a first direction;
forming a second gate electrode over the second active region, the fourth active region and the device isolation insulating film, extending in the first direction;
forming a third gate electrode over the first active region, extending in the first direction;
forming a fourth gate electrode over the second active region, extending in the first direction;
forming a first insulating film over the first gate electrode, the second gate electrode, the third gate electrode and the fourth gate electrode;
forming a first hole, a second hole, a third hole, a fourth hole, a fifth hole and a sixth hole penetrating through the first insulating film, the first hole exposing the second gate electrode and the third active region, the third hole exposing the first gate electrode and the fourth active region, the second hole between the first gate electrode and the third gate electrode exposing the first active region, the fourth hole between the second gate electrode and the fourth gate electrode exposing the second active region, the fifth hole in a side of the semiconductor device opposite to the first hole across the first gate electrode exposing the third active region, the sixth hole in the side of the semiconductor device opposite to the third hole across the second gate electrode exposing the fourth active region;
forming a first trench and a second trench in the first insulating film, the first trench being over the first hole and the second hole, the second trench being over the third hole and the fourth hole;
forming a first plug, a second plug, a third plug, a fourth plug, a fifth plug, a sixth plug, a first interconnection and a second interconnection by embedding a metal in the first hole, the second hole, the third hole, the fourth hole, the fifth hole, the sixth hole, the first trench and the second trench, respectively, the first plug having contact with the second gate electrode and the third active region, the second plug having contact with the first active region, the third plug having contact with the first gate electrode and the fourth active region, the fourth plug having contact with the second active region, the fifth plug having contact with the third active region, the sixth plug having contact with the fourth active region, the first interconnection having contact with the first plug and the second plug, the second interconnection having contact with the third plug and the fourth plug.

9 more elements

A method of manufacturing a semiconductor device comprising:

defining, in a semiconductor substrate, a first active region and a second active region by forming a device isolation insulating film in the semiconductor substrate;
defining, in the semiconductor substrate, a third active region and a fourth active region between the first active region and the second active region, by the forming the device isolation insulating film in the semiconductor substrate;
implanting a p-type ion in the first active region and the second active region;
implanting a n-type ion in the third active region and the fourth active region;
forming a first gate electrode over the first active region, the third active region and the device isolation insulating film, extending in a first direction;
forming a second gate electrode over the second active region, the fourth active region and the device isolation insulating film, extending in the first direction;
forming a third gate electrode over the first active region, extending in the first direction;
forming a fourth gate electrode over the second active region, extending in the first direction;
forming a first insulating film over the first gate electrode, the second gate electrode, the third gate electrode and the fourth gate electrode;
forming a first hole, a second hole, a third hole and a fourth hole penetrating through the first insulating film, the first hole exposing the second gate electrode and the third active region, the third hole exposing the first gate electrode and the fourth active region, the second hole between the first gate electrode and the third gate electrode exposing the first active region, the fourth hole between the second gate electrode and the fourth gate electrode exposing the second active region;
forming a first plug, a second plug, a third plug and a fourth plug by embedding a metal in the first hole, the second hole, the third hole and the fourth hole, respectively, the first plug having contact with the second gate electrode and the third active region, the second plug having contact with the first active region, the third plug having contact with the first gate electrode and the fourth active region, the fourth plug having contact with the second active region;
forming a second insulating film over the first insulating film, the first plug, the second plug, the third plug and the fourth plug;
forming a fifth hole and a sixth hole in the first insulating film and the second insulating film by etching the first insulating film and the second insulating film at a time, the fifth hole in a side of the semiconductor device opposite to the first hole across the first gate electrode, exposing the third active region, the sixth hole in the side of the semiconductor device opposite to the third hole across the second gate electrode, exposing the fourth active region;
forming a first trench and a second trench in the first insulating, the first trench exposing the first plug and the second plug, the second trench exposing the third plug and the fourth plug;
forming a fifth plug, a sixth plug, a first interconnection and a second interconnection by embedding a metal in the fifth hole, the sixth hole, the first trench and the second trench, respectively, the fifth plug having contact with the third active region, the sixth plug having contact with the fourth active region, the first interconnection having contact with the first plug and the second plug, the second interconnection having contact with the third plug and the fourth plug.

12 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/584,253Filed 13 Aug 2012 · division
Priority: JP 2009-1608377 Jul 2009
Published: US 2012/0309143 A16 Dec 2012
Granted: 29 Oct 2013
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

H10B 10/12
Static random access memory [SRAM] devices: comprising a MOSFET load element
G11C 11/412
Forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt…
H10B 10/00
Static random access memory [sram] devices
H10D 89/10
Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00: integrated device layouts