# US 8,569,121 B2 · Graphene and nanotube/nanowire transistor with a self-aligned gate structure on transparent substrates and method of making same

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- Number: US 8,569,121 B2
- Document ID: US8569121B2
- Status: Granted
- Kind: B2
- Application number: 13/286,394
- Filed: 2011-11-01
- Published: 2013-05-02
- Granted: 2013-10-29
- Earliest claimed: 2011-11-01
- Assignees: International Business Machines Corporation
- Applicants: Wilfried Ernst-August Haensch; Zihong Liu
- Inventors: Wilfried Ernst-August Haensch; Zihong Liu
- Web page: https://patentgrep.com/patent/US8569121B2

## CPC

- H10D 62/812: {Single quantum well structures}
- H10D 12/031: {of IGBTs}
- H10D 30/015: {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT}
- H10D 30/0215: {using self-aligned selective metal deposition simultaneously on gate electrodes and the source regions or drain regions}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/472: {having lower bandgap active layer formed on top of wider bandgap layer, e.g. inverted HEMT}
- H10D 30/481: {FETs having two-dimensional material channels, e.g. transition metal dichalcogenide [TMD] FETs}
- H10D 30/6741: {Group IV materials, e.g. germanium or silicon carbide (TFTs having oxide semiconductors H10D30/6755)}
- H10D 62/119: {Nanowire, nanosheet or nanotube semiconductor bodies}
- H10D 62/8325: {Silicon carbide}
- H10D 62/882: {Graphene}
- H10D 64/514: {characterised by the insulating layers}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D 64/60: Electrodes characterised by their materials
- H10P 14/40: of conductive or resistive materials
- H10P 34/422: {using incoherent radiation}
- H10P 50/691: {for Group IV materials or Group III-V materials}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Transistor devices having a self-aligned gate structure on transparent substrates and techniques for fabrication thereof are provided. In one aspect, a method of fabricating a transistor device includes the following steps. A channel material is formed on a transparent substrate. Source and drain electrodes are formed in contact with the channel material. A dielectric layer is deposited on the channel material. A photoresist is deposited on the dielectric layer and developed using UV light exposure through the transparent substrate. A gate metal(s) is deposited on the exposed portions of the dielectric layer and the undeveloped portions of the photoresist. The undeveloped portions of the photoresist are removed along with portions of the gate metal over the source and drain regions to form a gate of the device on the dielectric layer over the channel material which is self-aligned to the source and drain electrodes.

## Claims

### Claim 1

A method of fabricating a transistor device, comprising the steps of:
providing a transparent substrate;
forming a channel material on the substrate;
forming source and drain electrodes over, and in contact with, the channel material;
depositing a photoresist on the channel material and on the source and drain electrodes;
developing the photoresist using UV light exposure through the transparent substrate, wherein exposure of portions of the photoresist is blocked by the source and drain electrodes;
removing developed portions of the photoresist exposing portions of the channel material, wherein undeveloped portions of the photoresist remain over the source and drain electrodes;
depositing a dielectric layer on the channel material and on the undeveloped portions of the photoresist to a thickness of from about 1 nm to about 100 nm, wherein the dielectric layer is deposited after the photoresist has been developed through the substrate and after the developed portions of the photoresist have been removed;
depositing at least one gate metal on the dielectric layer; and
removing the undeveloped portions of the photoresist along with portions of the gate metal and portions of the dielectric layer over the source and drain regions, wherein a remaining portion of the gate metal between the source and drain region electrodes forms a gate of the device on the dielectric layer over the channel material which is self-aligned to the source and drain electrodes.

### Claim 2 (depends on 1)

The method of claim 1, wherein the transparent substrate comprises a glass substrate, a flexible plastic substrate or a silicon carbide wafer.

### Claim 3 (depends on 1)

The method of claim 1, wherein the channel material comprises a carbon-based material.

### Claim 4 (depends on 3)

The method of claim 3, wherein the carbon-based material comprises graphene or carbon nanotubes.

### Claim 5 (depends on 1)

The method of claim 1, wherein the channel material comprises a nanostructured material selected from the group consisting of nanowires, nanorods, nanocolumns and quantum dots.