Method for manufacturing thin film transistor

A method for manufacturing a thin film transistor, comprising:

• forming a gate electrode over a substrate;
• forming a gate insulating layer over the gate electrode;
• forming a first semiconductor layer over the gate insulating layer by applying high frequency power using a first mixed gas containing hydrogen, and a rare gas, and at least one of silicon and germanium;
• forming a second semiconductor layer including the first semiconductor layer and an amorphous semiconductor over the gate insulating layer by applying high frequency power using a second mixed gas containing hydrogen, a gas containing nitrogen, and at least one of silicon and germanium after forming the first semiconductor layer;
• forming an impurity semiconductor layer over the second semiconductor layer;
• etching the second semiconductor layer and the impurity semiconductor layer;
• forming a conductive layer;
• forming a wiring by etching the conductive layer;
• and
• forming source and drain regions by etching the etched impurity semiconductor layer formed by the step of etching the second semiconductor layer and the impurity semiconductor layer.

A method for manufacturing a thin film transistor, comprising:

• forming a gate electrode over a substrate;
• forming a gate insulating layer over the gate electrode;
• forming a first semiconductor layer over the gate insulating layer by applying high frequency power using a first mixed gas containing hydrogen, a rare gas, and at least one of silicon and germanium;
• forming a second semiconductor layer including the first semiconductor layer and an amorphous semiconductor over the gate insulating layer by applying high frequency power using a second mixed gas containing hydrogen, a gas containing nitrogen, and at least one of silicon and germanium after forming the first semiconductor layer;
• forming an impurity semiconductor layer over the second semiconductor layer;
• forming a conductive layer over the impurity semiconductor layer;
• etching the second semiconductor layer, the impurity semiconductor layer, and the conductive layer;
• forming a wiring by etching the etched conductive layer;
• and
• forming source and drain regions by etching the etched impurity semiconductor layer formed by the step of etching the second semiconductor layer and the impurity semiconductor layer.