Systems and methods integrating trench-gated thyristor with trench-gated rectifier
AssigneePakal Technologies, Inc.
InventorsHidenori Akiyama, Richard A. Blanchard, Woytek Tworzydlo
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Abstract
An integrated trench-MOS-controlled-thyristor plus trench gated diode combination, in which the trenches are preferably formed at the same time. A backside polarity reversal process permits a backside p+ region in the thyristor areas, and only a backside n+ region in the diode areas (for an n-type device). This is particularly advantageous in motor control circuits and the like, where the antiparallel diode permits the thyristor to be dropped into existing power MOSFET circuit designs. In power conversion circuits, the antiparallel diode can conveniently serve as a freewheeling diode.
Claims20
A method of manufacturing both a thyristor and also a high-current diode on a single semiconductor die, comprising:
- forming a heavily-doped first-conductivity-type region at a front surface of the semiconductor die, both in a thyristor location and also simultaneously in a diode location;
- forming trenches into the semiconductor die, both in the thyristor location and also simultaneously in the diode location;
- insulating said trenches;
- forming a second-conductivity-type base region, in said thyristor location but not in said diode location, which forms a junction with underlying first-conductivity-type semiconductor material at a depth which is deeper than said trenches;
- forming a second-conductivity-type body region, in at least said diode location, which forms a junction with said underlying first-conductivity-type semiconductor material at a depth which is not significantly deeper than the bottoms of said trenches;
- after the insulating step, forming a first gate electrode inside said trenches in the thyristor location, and forming a second gate electrode which is not connected to said first gate electrode inside said trenches in the diode location;
- forming a heavily-doped first-conductivity-type backside contact region beneath said diode location, and a heavily-doped second-conductivity-type backside contact region beneath said thyristor location;
- and
- forming a first metallic layer which connects to said heavily-doped first-conductivity-type region in both the thyristor location and diode location, and forming a second metallic layer which connects to both said heavily-doped first-conductivity-type backside contact region and also to said heavily-doped second-conductivity-type backside contact region.
A method of manufacturing both a thyristor and also a high-current diode on a single semiconductor die, comprising:
- forming a heavily-doped first-conductivity-type region at a front surface of the semiconductor die in a thyristor location;
- forming a heavily-doped first-conductivity-type region at a front surface of the semiconductor die in a diode location;
- forming trenches into the semiconductor die in the thyristor location;
- forming trenches into the semiconductor die in the diode location;
- insulating said trenches, wherein said insulating step in said thyristor location is performed differently than in said diode location;
- forming a second-conductivity-type base region, in said thyristor location but not in said diode location, which forms a junction with underlying first-conductivity-type semiconductor material at a depth which is deeper than said trenches;
- forming a second-conductivity-type body region, in at least said diode location, which forms a junction with said underlying first-conductivity-type semiconductor material at a depth which is not significantly deeper than the bottoms of said trenches;
- after the insulating step, forming a first gate electrode inside said trenches in the thyristor location, and forming a second gate electrode which is not connected to first gate electrode inside said trenches in the diode location;
- forming a heavily-doped first-conductivity-type backside contact region beneath said diode location, and a heavily-doped second-conductivity-type backside contact region beneath said thyristor location;
- and
- forming a first metallic layer which connects to said heavily-doped first-conductivity-type region in both the thyristor location and diode location, and forming a second metallic layer which connects to both said heavily-doped first-conductivity-type backside contact region and to said heavily-doped second-conductivity-type backside contact region.
A method of manufacturing both a thyristor and also a high-current diode on a single semiconductor die, comprising:
- forming a heavily-doped first-conductivity-type region at a front surface of the semiconductor die in a thyristor location;
- forming a heavily-doped first-conductivity-type region at a front surface of the semiconductor die in a diode location;
- forming trenches into the semiconductor die, both in the thyristor location and also simultaneously in the diode location;
- insulating said trenches;
- forming a second-conductivity-type base region, in said thyristor location but not in said diode location, which forms a junction with underlying first-conductivity-type semiconductor material at a depth which is deeper than said trenches;
- forming a second-conductivity-type body region, in at least said diode location, which forms a junction with said underlying first-conductivity-type semiconductor material at a depth which is not significantly deeper than the bottoms of said trenches;
- after the insulating step, forming a first gate electrode inside said trenches in the thyristor location;
- and forming a second gate electrode which is not connected to first gate electrode inside said trenches in the diode location;
- forming a heavily-doped first-conductivity-type backside contact region beneath said diode location, and a heavily-doped second-conductivity-type backside contact region beneath said thyristor location;
- and
- forming a first metallic layer which connects to said heavily-doped first-conductivity-type region in both the thyristor location and diode location, and forming a second metallic layer which connects to both said heavily-doped first-conductivity-type backside contact region and also to said heavily-doped second-conductivity-type backside contact region.
Dependencies are inferred from the claim text.