# US 8,569,115 B1 · Method of forming a compliant bipolar micro device transfer head with silicon electrodes

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- Number: US 8,569,115 B1
- Document ID: US8569115B1
- Status: Granted
- Kind: B1
- Application number: 13/543,680
- Filed: 2012-07-06
- Granted: 2013-10-29
- Earliest claimed: 2012-07-06
- Assignees: LuxVue Technology Corporation
- Applicants: Dariusz Golda; Andreas Bibl
- Inventors: Dariusz Golda; Andreas Bibl
- Web page: https://patentgrep.com/patent/US8569115B1

## CPC

- H10P 72/722: {Details of electrostatic chucks}
- B32B 38/18: Handling of layers or the laminate
- B81C 99/002: {Apparatus for assembling MEMS, e.g. micromanipulators (micromanipulators per se B25J7/00)}
- H02N 13/00: Clutches or holding devices using electrostatic attraction, e.g. using Johnson-Rahbek effect
- H10D 62/10: Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D 62/106: {having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions}
- H10D 62/126: {Top-view geometrical layouts of the regions or the junctions}
- H10P 30/22: using masks
- H10P 50/693: {characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane}
- H10P 90/1906: {Preparing SOI wafers}
- H10W 10/061: {using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations}
- H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers}
- H10D 8/051: {of Schottky diodes}
- H10D 8/60: Schottky-barrier diodes
- H10D 8/605: {of the trench conductor-insulator-semiconductor barrier type, e.g. trench MOS barrier Schottky rectifiers [TMBS]}
- H10D 12/038: {having a recessed gate, e.g. trench-gate IGBTs}
- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs}
- H10D 64/117: {Recessed field plates, e.g. trench field plates or buried field plates}
- H10D 84/146: {the built-in components being Schottky barrier diodes}
- H10W 72/0711: {Apparatus therefor}
- Y10T 156/17: Surface bonding means and/or assemblymeans with work feeding or handling means
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- B32B: LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B81C: PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS (making microcapsules or microballoons B01J13/02; processes or apparatus specially adapted for the manufacture or treatment of piezoelectric, electrostrictive or magnetostrictive elements per se H10N30/01)
- H02N: ELECTRIC MACHINES NOT OTHERWISE PROVIDED FOR
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- Y10T: TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION

## Abstract

A compliant bipolar micro device transfer head array and method of forming a compliant bipolar micro device transfer array from an SOI substrate are described. In an embodiment, a compliant bipolar micro device transfer head array includes a base substrate and a patterned silicon layer over the base substrate. The patterned silicon layer may include first and second silicon interconnects, and first and second arrays of silicon electrodes electrically connected with the first and second silicon interconnects and deflectable into one or more cavities between the base substrate and the silicon electrodes.

## Claims

### Claim 1

A method of forming a compliant bipolar transfer head array comprising:
etching a top silicon layer of a silicon-on-insulator stack to form a first array of silicon electrodes electrically connected with a first silicon interconnect, and a second array of silicon electrodes aligned with the first array of silicon electrodes and electrically connected with a second silicon interconnect to form an array of bipolar silicon electrode pairs, each silicon electrode in the first and second arrays of silicon electrodes including an electrode lead and a mesa structure that protrudes above the first and second silicon interconnects;
forming a dielectric layer over the first and second arrays of silicon electrodes; and
etching one or more cavities in the base substrate directly underneath the first and second arrays of silicon electrodes such that each silicon electrode in the first and second arrays of silicon electrodes is deflectable into the one or more cavities.

### Claim 2 (depends on 1)

The method of claim 1, wherein etching one or more cavities in the base substrate comprises reactive ion etching with a fluorinated plasma selected from the group consisting of SF6 and XeF2.

### Claim 3 (depends on 1)

The method of claim 1, wherein etching one or more cavities in the base substrate comprises etching a separate cavity in the base substrate directly underneath each bipolar silicon electrode pair.

### Claim 4 (depends on 1)

The method of claim 1, wherein etching one or more cavities in the base substrate comprises etching a single cavity in the base substrate directly underneath the array of bipolar silicon electrode pairs.

### Claim 5 (depends on 4)

The method of claim 4, further comprising etching the single cavity in the base substrate such that it wraps around an end of one of the first and second silicon interconnects.

### Claim 6 (depends on 1)

The method of claim 1, wherein etching the top silicon layer of the silicon-on-insulator stack exposes a buried oxide layer.

### Claim 7 (depends on 6)

The method of claim 6, further comprising forming a patterned layer over the buried oxide layer and the dielectric layer after forming the dielectric layer over the first and second arrays of silicon electrodes, and etching through the buried oxide layer to expose a portion of the base substrate.

### Claim 8 (depends on 7)

The method of claim 7, further comprising etching the one or more cavities in the base substrate directly underneath the first and second arrays of silicon electrodes using the dielectric layer as an etching mask.

### Claim 9 (depends on 6)

The method of claim 6, wherein forming the dielectric layer comprises thermal oxidation of the first and second arrays of silicon electrodes.

### Claim 10 (depends on 6)

The method of claim 6, further comprising etching an array of joint trenches between the mesa structures of the first and second arrays of silicon electrodes simultaneously with etching the top silicon layer of the silicon-on-insulator stack to form the first and second arrays of silicon electrodes, wherein etching the array of joint trenches exposes the buried oxide layer.

### Claim 11 (depends on 10)

The method of claim 10, further comprising forming the dielectric layer within the array of joint trenches and in direct contact with the buried oxide layer simultaneously with forming the dielectric layer over the first and second arrays of silicon electrodes.

### Claim 12 (depends on 11)

The method of claim 11, wherein forming the dielectric layer comprises thermal oxidation of the first and second arrays of silicon electrodes.

### Claim 13 (depends on 12)

The method of claim 12, further comprising completely filling the array of joint trenches with the dielectric layer to form an array of oxide joints between the first and second arrays of silicon electrodes.

### Claim 14 (depends on 6)

The method of claim 6, further comprising etching a first backside via opening through the base substrate directly underneath the first silicon interconnect, and etching a second backside via opening through the base substrate directly underneath the second silicon interconnect.

### Claim 15 (depends on 14)

The method of claim 14, further comprising, forming a passivation layer within the first and second backside via openings, wherein forming the passivation layer comprises simultaneously thermally oxidizing the first and second arrays of silicon electrodes and the base substrate within the first and second backside via openings.

### Claim 16 (depends on 15)

The method of claim 15, further comprising forming a patterned conductive layer within the first and second via openings to make electrical contact with the first and second silicon interconnects.

### Claim 17 (depends on 16)

The method of claim 16, wherein forming the patterned conductive layer comprises depositing the patterned conductive layer through a shadow mask.

### Claim 18 (depends on 7)

The method of claim 7, further comprising etching through the dielectric layer to expose a first portion of the first silicon interconnect and a second portion of the second silicon interconnect simultaneously with etching through the buried oxide layer to expose the portion of the base substrate.

### Claim 19 (depends on 18)

The method of claim 18, further comprising etching a first topside via opening through the exposed first portion of the first silicon interconnect and the buried oxide layer, etching a second topside via opening through the exposed second portion of the second silicon interconnect and the buried oxide layer, and forming a patterned conductive layer within the first and second topside via openings to make electrical contact with the first and second silicon interconnects.

### Claim 20 (depends on 7)

The method of claim 7, further comprising etching through the dielectric layer to expose each of the mesa structures simultaneously with etching through the buried oxide layer to expose the portion of the base substrate.

### Claim 21 (depends on 20)

The method of claim 20, further comprising forming a patterned second dielectric layer over each of the mesa structures.

### Claim 22 (depends on 21)

The method of claim 21, wherein forming the patterned second dielectric layer comprises blanket depositing the second dielectric layer, and removing a portion of the second dielectric layer.

### Claim 23 (depends on 22)

The method of claim 22, wherein blanket depositing the second dielectric layer comprises atomic layer deposition.

### Claim 24 (depends on 7)

The method of claim 7, further comprising etching through the dielectric layer to expose a first portion of the first silicon interconnect, a second portion of the second silicon interconnect, and each of the mesa structures simultaneously with etching through the buried oxide layer to expose the portion of the base substrate.

### Claim 25 (depends on 24)

The method of claim 24, further comprising etching a first topside via opening through the exposed first portion of the first silicon interconnect and the buried oxide layer, etching a second topside via opening through the exposed second portion of the second silicon interconnect and the buried oxide layer, and forming a patterned conductive layer within the first and second topside via openings to make electrical contact with the first and second silicon interconnects.

### Claim 26 (depends on 25)

The method of claim 25, wherein etching the one or more cavities further comprises using the second dielectric layer formed over each of the mesa structures and the conductive layer formed within the first and second topside via openings as an etching mask.