Method of forming a semiconductor device package
AssigneeSamsung Electronics Co., Ltd.
InventorsChoongbin Yim, Seungkon Mok, Donghan Kim, Jin-Woo Park, PaLan Lee, Mi-yeon Kim
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Abstract
Provided is a method of forming a semiconductor package. In the method, a first package including a first chip on a first substrate is formed, a second package including a second chip on a second substrate is formed, a molding cap provided with a via hole and a recess structure configured to receive the first chip is formed, and the second package is provided on the first package with the molding cap being therebetween such that the recess receives the first chip. The via hole and the recess structure are simultaneously formed.
Claims18
A method of forming a semiconductor package, the method comprising:
- forming a first package including a first chip on a first substrate;
- forming a second package including a second chip on a second substrate;
- forming a moulding cap provided with a via hole and a recess structure configured to receive the first chip, wherein the via hole and the recess structure are simultaneously formed and wherein the moulding cap is formed separately from the first package and the second package;
- providing the second package on the first package with the moulding cap being therebetween such that the recess structure receives the first chip;
- and
- providing a contact in the via hole connecting the first package and the second package, wherein the contact is in direct physical contact with the moulding cap.
A method of forming a semiconductor package, the method comprising:
- forming a first package including a first chip on a first substrate by mounting the first chip on the first substrate, electrically connecting the first substrate to the first chip through bonding bumps or bonding wires and forming a passivation material between the first substrate and the first chip and on a sidewall of the first chip;
- forming a second package including a second chip on a second substrate by mounting the second chip on the second substrate, electrically connecting the second substrate to the second chip through bonding bumps or bonding wires and forming a passivation material on the second substrate to mould the second chip;
- forming a moulding cap provided with via holes and a recess structure configured to receive the first chip, wherein the molding cap is formed using a mould comprising an upper mould and a lower mould and by injecting an epoxy moulding compound (EMC) into a formation region between the upper mould and the lower mould and then curing the EMC, wherein the lower mould is provided with a first projection for forming the recess structure and the upper mold is provided with a second projection for forming the via holes, and wherein the moulding cap is formed separately from the first package and the second package;
- adhering the moulding cap to an upper surface of the first package by an adhesive such that the recess structure receives the first chip therein;
- providing the second package on a top surface of the moulding cap adhered to the first package such that the moulding cap is disposed between the first package and the second package;
- providing a solder ball into at least one of the via holes of the moulding cap;
- and
- forming a contact in the at least one of the via holes of the moulding cap by performing a reflow process on the solder ball, thereby connecting the first package and the second package, wherein the contact is in direct physical contact with the moulding cap.
Dependencies are inferred from the claim text.