# US 8,569,112 B2 · Integrated circuit packaging system with encapsulation and leadframe etching and method of manufacture thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,569,112 B2 - Document ID: US8569112B2 - Status: Granted - Kind: B2 - Application number: 13/425,277 - Filed: 2012-03-20 - Published: 2013-09-26 - Granted: 2013-10-29 - Earliest claimed: 2012-03-20 - Assignees: STATS ChipPAC, Ltd. - Applicants: Byung Tai Do; Arnel Senosa Trasporto; Linda Pei Ee Chua - Inventors: Byung Tai Do; Arnel Senosa Trasporto; Linda Pei Ee Chua - Web page: https://patentgrep.com/patent/US8569112B2 ## CPC - H10W 74/111: {the semiconductor body being completely enclosed} - H10W 70/042: {Etching} - H10W 70/424: {Cross-sectional shapes (H10W70/481 takes precedence)} - H10W 70/457: {of metallic layers on leadframes} - H10W 70/687: {characterized by the outer layers being for protection, e.g. solder masks, or for protection against chemical or mechanical damage} - H10W 90/00: Package configurations - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 70/681: {comprising holes not having chips therein, e.g. for outgassing, underfilling or bond wire passage} - H10W 72/075: {of bond wires} - H10W 72/884: {Die-attach connectors and bond wires} - H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)} - H10W 74/10: characterised by their shape or disposition - H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body} - H10W 90/288: {characterised by arrangements for thermal management of the stacked chips} - H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A method of manufacture of an integrated circuit packaging system includes: providing a leadframe having a mounting region; applying a mounting structure in the mounting region; mounting an integrated circuit die on the mounting structure; forming an encapsulation on the integrated circuit die and having an encapsulation cavity, the encapsulation cavity shaped by the mounting structure; forming a lead having a lead protrusion from the leadframe, the lead protrusion below a horizontal plane of the integrated circuit die; and removing the mounting structure for exposing the integrated circuit die. ## Claims ### Claim 1 A method of manufacture of an integrated circuit packaging system comprising: providing a leadframe having a mounting region; applying a mounting structure in the mounting region; mounting an integrated circuit die on the mounting structure; forming an encapsulation on the integrated circuit die and having an encapsulation cavity, the encapsulation cavity shaped by the mounting structure; forming a lead having a lead protrusion from the leadframe, the lead protrusion below a horizontal plane of a bottom of the integrated circuit die; and completely removing the mounting structure for exposing the bottom of the integrated circuit die. ### Claim 2 (depends on 1) The method as claimed in claim 1 wherein forming the encapsulation includes forming the encapsulation cavity having a cavity horizontal dimension larger than a die horizontal dimension of the integrated circuit die. ### Claim 3 (depends on 1) The method as claimed in claim 1 wherein forming the encapsulation includes forming the encapsulation cavity having the lead protrusion extend to the encapsulation cavity. ### Claim 4 (depends on 1) The method as claimed in claim 1 further comprising: providing a base substrate; mounting a base integrated circuit to the base substrate; and mounting the base substrate to the lead with the base integrated circuit in the encapsulation cavity and the integrated circuit die over the base integrated circuit. ### Claim 5 (depends on 1) The method as claimed in claim 1 wherein: providing the leadframe includes providing the leadframe having a leadframe hole at the mounting region; and further comprising: applying a lead tape to a leadframe bottom side of the leadframe; and removing the lead tape for exposing the mounting structure. ### Claim 6 A method of manufacture of an integrated circuit packaging system comprising: providing a leadframe having a mounting region and plating a lead; applying a mounting structure in the mounting region; mounting an integrated circuit die on the mounting structure; forming an encapsulation on the integrated circuit die and having an encapsulation cavity, the encapsulation cavity shaped by the mounting structure; forming the lead having a lead protrusion from the leadframe, the lead protrusion below a horizontal plane of a bottom of the integrated circuit die; and completely removing the mounting structure for exposing the bottom of the integrated circuit die. ### Claim 7 (depends on 6) The method as claimed in claim 6 wherein forming the lead includes forming the lead partially in the encapsulation with only a portion of the lead at a lead bottom side exposed from the encapsulation. ### Claim 8 (depends on 6) The method as claimed in claim 6 wherein forming the encapsulation includes forming the encapsulation cavity bounded by a cavity sidewall, the cavity sidewall is orthogonal to the horizontal plane of the integrated circuit die. ### Claim 9 (depends on 6) The method as claimed in claim 6 further comprising connecting a chip interconnect between the integrated circuit die and the lead. ### Claim 10 (depends on 6) The method as claimed in claim 6 wherein: providing the leadframe includes providing a thin leadframe layer for mounting the mounting structure thereon; and further comprising: removing the thin leadframe layer with an etching process.