# US 8,567,051 B2 · Process for the vertical interconnection of 3D electronic modules by vias

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 8,567,051 B2
- Document ID: US8567051B2
- Status: Granted
- Kind: B2
- Application number: 12/258,060
- Filed: 2008-10-24
- Published: 2009-10-22
- Granted: 2013-10-29
- Earliest claimed: 2007-10-26
- Assignees: 3D Plus
- Applicants: Christian Val
- Inventors: Christian Val
- Web page: https://patentgrep.com/patent/US8567051B2

## CPC

- H10P 74/273: {Interconnections for measuring or testing, e.g. probe pads}
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/2125: {Top-view shapes}
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 72/0198: {batch processes}
- H10W 74/014: {using batch processing}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 90/00: Package configurations
- H10P 72/7422: {used to protect an active side of a device or wafer}
- H10P 72/7434: {used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 72/823: {Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip}
- H10W 72/874: {On different surfaces}
- H10W 72/9413: {on encapsulations}
- H10W 74/114: {by a substrate and the encapsulations}
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 90/10: Configurations of laterally-adjacent chips
- H10W 90/20: Configurations of stacked chips
- H10W 90/721: {of bump connectors}
- H10W 90/722: {between stacked chips}
- Y10T 29/49126: Assembling bases
- Y10T 29/4913: Assembling to base an electrical component, e.g., capacitor, etc.
- Y10T 29/49155: Manufacturing circuit on or in base
- Y10T 29/49165: by forming conductive walled aperture in base
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- Y10T: TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION

## Abstract

A process for the vertical interconnection of 3D electronic modules (100), a module comprising a stack of K electronic wafer levels (19) electrically connected together by conductors lying along the direction of the stack that is perpendicular to the plane of a wafer.

## Claims

### Claim 1

Process for the vertical interconnection of n 3D electronic modules, n being an integer greater than 1, each 3D electronic module comprising a stack of K electronic, wafer levels, K being an integer, a wafer level i, i being an integer varying from 1 to K, comprising at least one electronic component, the K wafer levels being electrically connected together by conductors lying along the direction of the stack that is perpendicular to the plane of a wafer, for each wafer level i, comprising:
a. fabricating a batch of n wafer levels, a wafer level comprising at least it geometric features bounded by dicing lines, each geometric feature comprising at least one electronic component surrounded by insulating resin and connected to electrical connection pads, the electrical connection pads being connected to electrical connection tracks deposited on a dielectric layer, wherein each electrical connection track extends as far as an electrode interconnecting the electrical connection tracks and located on the dicing lines, and comprises a curved segment placed between two straight segments, the curved segment defining a zone that surrounds a location intended to form a via, this zone being placed between the electrical connection pad and the track interconnection electrode;
b. stacking and assembling the K wafer levels obtained after the first step so as to superpose said zones approximately one on top of another;
c. drilling vias in the resin along the direction of the stack and over the entire thickness of the stack, at the latter plumb with the locations of the vias, the cross section of the vias being such that, for each wafer level, the straight segments are flush with the vias but not with the curved segments;
d. metallizing the wall of each via by electrolytic growth; and
e. cutting the stack along the dicing lines, the width of the cuts being greater than that of the track interconnection electrode, so as to obtain the n 3D electronic modules.

### Claim 2 (depends on 1)

The process according to claim 1, wherein at least one of the straight segments has a protrusion inside said zone.

### Claim 3 (depends on 1)

Process according to the preceding claim 1 wherein the metal of the vias is selected from the group comprising copper, nickel, gold, silver and tin.

### Claim 4 (depends on 1)

Process according to claim 1, wherein that the curved segment is selected from the group comprising a circular arc, a circle, an elliptical arc or an ellipse, a half-triangle or a triangle, and a half-rectangle or a rectangle.

### Claim 5 (depends on 1)

Process according to claim 1, wherein the electronic component is selected from the group comprising an active component, a passive component and a MEMS.

### Claim 6 (depends on 1)

Process according to claim 1, wherein at least one passive component is located in the wafer or on the wafer.

### Claim 7 (depends on 1)

Process according to claim 1, wherein the vias are formed by laser dry etching or plasma dry etching.

### Claim 8 (depends on 1)

Process according to claim 1, wherein the vias are formed by wet etching.