US 8,560,757 B2 · System and method to reduce memory access latencies using selective replication across multiple memory ports

Abstract

In one embodiment, a system includes memory ports distributed into subsets identified by a subset index, where each memory port has an individual wait time based on a respective workload. The system further comprises a first address hashing unit configured to receive a read request including a virtual memory address associated with a replication factor and referring to graph data. The first address hashing unit translates the replication factor into a corresponding subset index based on the virtual memory address, and converts the virtual memory address to a hardware based memory address referring to graph data in the memory ports within a subset indicated by the corresponding subset index. The system further comprises a memory replication controller configured to direct read requests to the hardware based address to the one of the memory ports within the subset indicated by the corresponding subset index with a lowest individual wait time.

Claims27

Dependent claims

A system comprising:

a plurality of memory ports, the plurality of memory ports distributed into a plurality of subsets, each subset identified by a subset index, each of the plurality of memory ports having an individual wait time based on a respective workload;
a first address hashing unit configured to receive a read request including a virtual memory address, the virtual memory address associated with a replication factor, the virtual memory address referring to graph data, translate the replication factor into a corresponding subset index based on the virtual memory address, and convert the virtual memory address to a hardware based memory address, the hardware based address referring to graph data in at least one of the memory ports within a subset indicated by the corresponding subset index;
a memory replication controller configured to direct read requests to the hardware based address to the one of the plurality of memory ports within the subset indicated by the corresponding subset index with a lowest individual wait time.

A method comprising:

distributing a plurality of memory ports into a plurality of subsets, each subset identified by a subset index, each of the plurality of memory ports having an individual wait time based on a respective work load;
receiving a read request, at a first address hashing unit, with a virtual memory address and a replication factor, the virtual memory address referring to graph data;
translating, at the first address hashing unit, the replication factor into a corresponding subset index based on the virtual memory address;
converting, at the first address hashing unit, the virtual memory address to a hardware based memory address, the hardware based address referring to a separate one of the plurality of memory ports within a subset indicated by the corresponding subset index;
directing read requests, in a memory replication controller, to the hardware based address to the one of the plurality of memory ports with a lowest individual wait time.

2 more elements

Dependencies are inferred from the claim text.

System and method to reduce memory access latencies using selective replication across multiple memory ports

Life of this patent

System and method to reduce memory access latencies using selective replication across multiple memory ports

Life of this patent

Abstract

Claims27