Shift register

A shift register comprising:

• unit circuits in cascade connection,
• each unit circuit including,
• an output transistor provided between a clock terminal and an output terminal, the output transistor configured to switch between passing and blocking of a clock signal, provided to the clock terminal, according to a gate potential applied to a gate of the output transistor;
• and
• one or more control transistors each having a first conduction terminal, a second conduction terminal and a gate, the first conduction terminal of each control transistor being connected to the gate of the output transistor, the one or more control transistors including a first control transistor configured to reduce a leakage current during a clock passing period in which the output transistor is in an ON state and the clock signal has a high level potential, wherein
• during the clock passing period,
• the gate potential of the output transistor is higher than the high-level potential of the clock signal,
• a low-level potential is applied to the gate of the first control transistor to turn the first control transistor to an OFF state, and
• a low-level potential is applied to the second conduction terminal of the first control transistor;
• and
• the first control transistor has a channel length that is longer than a channel length of the output transistor.