Fractional-N dividers having divider modulation circuits therein with segmented accumulators

A fractional-N divider circuit, comprising:

• a multi-modulus divider configured to perform at least /N and /N+1 frequency division of a first reference signal received at a first input thereof in response to an overflow signal received at a second input thereof, where N is an integer greater than one;
• a phase correction circuit configured to generate a second reference signal in response to a divider output signal generated by said multi-modulus divider, said second reference signal having a duty cycle that is more nearly uniform relative to the divider output signal;
• and
• a divider modulation circuit configured to generate the overflow signal in response to a digital code that specifies a plurality of division moduli to be used by said multi-modulus divider during the at least /N and /N+1 frequency division of the first reference signal, said divider modulation circuit comprising a segmented accumulator configured to generate a plurality of segments of a count value having at least one period of latency therebetween, said segmented accumulator comprising a first accumulator segment responsive to a plurality of least significant bits of the digital code and last accumulator segment responsive to a plurality of most significant bits of the digital code.

A fractional-N divider circuit, comprising:

• a multi-modulus divider configured to perform at least /N and /N+1 frequency division of a first reference signal received at a first input thereof in response to an overflow signal received at a second input thereof, where N is an integer greater than one;
• a phase correction circuit configured to generate a second reference signal in response to a divider output signal generated by said multi-modulus divider, said phase correction circuit comprising:
• a duty cycle adjustment circuit responsive to the divider output signal and a feedback signal derived from the second reference signal;
• and
• a phase interpolator responsive to at least one signal generated by said duty cycle adjustment circuit;
• a divider modulation circuit configured to generate the overflow signal in response to a code that specifies a plurality of division moduli to be used by said multi-modulus divider during the at least /N and /N+1 frequency division of the first reference signal;
• and
• a phase error calculator configured to provide at least one segment of a count value generated by said divider modulation circuit to said phase correction circuit.

A fractional-N divider circuit, comprising:

• a multi-modulus divider configured to perform at least /N and /N+1 frequency division of a first reference signal received at a first input thereof in response to an overflow signal received at a second input thereof, where N is an integer greater than one;
• a phase correction circuit configured to generate a second reference signal in response to a divider output signal generated by said multi-modulus divider, said phase correction circuit comprising:
• a duty cycle adjustment circuit responsive to the divider output signal and a feedback signal derived from the second reference signal, said duty cycle adjustment circuit comprising a pair of latches having data terminals responsive to the feedback signal and clock terminals responsive to true and complementary versions of the divider output signal;
• and
• a phase interpolator responsive to at least one signal generated by said duty cycle adjustment circuit;
• and
• a divider modulation circuit configured to generate the overflow signal in response to a code that specifies a plurality of division moduli to be used by said multi-modulus divider during the at least /N and /N+1 frequency division of the first reference signal.

A fractional-N divider circuit, comprising:

• a multi-modulus divider configured to perform at least /N and /N+1 frequency division of a first reference signal received at a first input thereof in response to an overflow signal received at a second input thereof, where N is an integer greater than one;
• a phase correction circuit configured to generate a second reference signal in response to a divider output signal generated by said multi-modulus divider, said phase correction circuit comprising:
• a duty cycle adjustment circuit responsive to the divider output signal and a feedback signal derived from the second reference signal;
• and
• a phase interpolator responsive to at least one signal generated by said duty cycle adjustment circuit;
• and
• a divider modulation circuit configured to generate the overflow signal in response to a digital code that specifies a repeating sequence of division moduli to be used by said multi-modulus divider during the at least /N and /N+1 frequency division of the first reference signal, said divider modulation circuit comprising a segmented accumulator configured to generate a plurality of segments of a count value having at least one period of latency therebetween, said segmented accumulator comprising a first accumulator segment responsive to a plurality of least significant bits of the digital code and last accumulator segment responsive to a plurality of most significant bits of the digital code.