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US 8,559,581 B2Granted
CDR circuit, reception apparatus, and communication system
AssigneeSony Corporation
InventorsTomokazu Tanaka, Hidekazu Kikuchi
Life of this patent
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Abstract
Disclosed herein is a CDR circuit including delay elements, including: a divider having a delay element and configured to extract a clock by using, as a trigger, a data input with a signal transition regularly inserted; and a latch configured to latch an input data signal in synchronization with the clock extracted by the divider.
Claims17
A reception apparatus comprising:
- a Clock Data Recovery circuit, abbreviated as a CDR circuit, configured to receive a serial data signal propagated over a data line and regularly inserted with a signal transition to recover a clock and data in accordance with the received serial data signal, said CDR circuit including
- a divider having a delay element for extracting, as a trigger, a data input regularly inserted with a signal transition and
- a latch for latching an input data signal in synchronization with a clock extracted by said divider,
- wherein said divider has
- a flip-flop configured to enter data from a data input terminal of said flip-flop in synchronization with an input signal into a clock input terminal of said flip-flop and output the held data from a data output terminal of said flip-flop as an extraction clock, and
- one of one delay element connected to said data output terminal of said flip-flop and a plurality of delay elements cascaded to said data output terminal of said flip-flop;
- each of said delay elements outputs an extracted clock obtained by delaying an input clock;
- and
- an inverted signal of an output extracted clock of any one of said one delay element and said plurality of delay elements is supplied to said data input terminal of said flip-flop.
6 more elements
A clock data recovery circuit comprising:
- a clock input terminal of a divider flip-flop electrically connected to a supply line, said supply line being electrically connected to a data input terminal of a first latch flip-flop and to a data input terminal of a second latch flip-flop;
- a normal-side output terminal of the divider flip-flop electrically connected to a clock input terminal of the first latch flip-flop and to a normal-side input terminal of a first delay element, an input terminal of a phase comparator being electrically connected to said normal-side output terminal of the divider flip-flop.
Dependencies are inferred from the claim text.