Adaptive synchronization circuit
AssigneeOracle America, Inc.
InventorsTarik Ono, Mark R. Greenstreet
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Abstract
Embodiments of a synchronization circuit are described. This synchronization circuit includes multiple selectively coupled synchronization stages which are configurable to synchronize data and control signals between a first time domain and a second time domain, where the synchronization can be performed based on asynchronous or synchronous events associated with either the first time domain or the second time domain. Additionally, the synchronization circuit includes control logic, coupled to the synchronization stages, which is configured to adapt a number of synchronization stages used to synchronize the data and the control signals based on an estimate of a probability of metastability persisting to an output of the synchronization circuit during the synchronization.
Claims20
A synchronization circuit, comprising:
- multiple selectively coupled synchronization stages configurable to synchronize data and control signals between a first time domain and a second time domain, wherein the synchronization can be performed based on asynchronous or synchronous events associated with either the first time domain or the second time domain;
- multiple FIFO stages, wherein at least one of the FIFO stages includes an instance of the multiple selectively coupled synchronization stages, and wherein the multiple FIFO stages are configured to exchange a put token that determines which of the multiple FIFO stages services a request from a transmitter of at least some of the data and control signals;
- and
- control logic, coupled to the synchronization stages, configured to adapt a number of synchronization stages used to synchronize the data and the control signals based on an estimate of a probability of metastability persisting to an output of the synchronization circuit during synchronization.
A non-transitory computer-readable medium containing data representing a synchronization circuit, wherein the synchronization circuit includes:
- multiple selectively coupled synchronization stages configurable to synchronize data and control signals between a first time domain and a second time domain, wherein the synchronization can be performed based on asynchronous or synchronous events associated with either the first time domain or the second time domain;
- multiple FIFO stages, wherein at least one of the FIFO stages includes an instance of the multiple selectively coupled synchronization stages, and wherein the multiple FIFO stages are configured to exchange a put token that determines which of the multiple FIFO stages services a request from a transmitter of at least some of the data and control signals;
- and
- control logic, coupled to the synchronization stages, configured to adapt a number of synchronization stages used to synchronize the data and the control signals based on an estimate of a probability of metastability persisting to an output of the synchronization circuit during the synchronization.
A computer system comprising an integrated circuit, wherein the integrated circuit includes a synchronization circuit that contains:
- multiple selectively coupled synchronization stages configurable to synchronize data and control signals between a first time domain and a second time domain, wherein the synchronization can be performed based on asynchronous or synchronous events associated with either the first time domain or the second time domain;
- multiple FIFO stages, wherein at least one of the FIFO stages includes an instance of the multiple selectively coupled synchronization stages, and wherein the multiple FIFO stages are configured to exchange a put token that determines which of the multiple FIFO stages services a request from a transmitter of at least some of the data and control signals;
- and
- control logic, coupled to the synchronization stages, configured to adapt a number of synchronization stages used to synchronize the data and the control signals based on an estimate of a probability of metastability persisting to an output of the synchronization circuit during the synchronization.
Dependencies are inferred from the claim text.