Adaptation of delay line feedback equalizer
AssigneeLSI Corporation
InventorLizhi Zhong
Life of this patent
Estimating the term…
Abstract
An apparatus including an adder, a delay line, and a first detector. The adder may be configured to generate an input signal in response to a received signal and a feedback signal. The feedback signal may include a contribution from each of a plurality of delayed versions of the input signal. The contribution from each of the plurality of delayed versions of the input signal may be determined by a respective weight value. The delay line may be configured to generate the plurality of delayed versions of the input signal. The first detector may be configured to recover a data sample from the input signal in response to a clock signal.
Claims20
An apparatus comprising:
- an adder having a first input configured to receive an analog input signal, a second input configured to receive a feedback signal and an output configured to present an analog intermediate signal in response to said analog input signal and said feedback signal, wherein the feedback signal comprises a contribution from each of a plurality of delayed versions of said analog intermediate signal, and the contribution from each of said plurality of delayed versions of said analog intermediate signal is determined by a respective weight value;
- a delay line configured to generate said plurality of delayed versions of said analog intermediate signal;
- and
- a first detector configured to recover a digital data sample from said analog intermediate signal in response to a first clock signal.
An apparatus comprising:
- a delay line comprising a plurality of delay elements, wherein said delay line generates a plurality of delayed versions of an analog intermediate signal;
- an adder configured to generate said analog intermediate signal in response to an analog input signal and a feedback signal comprising a plurality of delayed versions of said analog intermediate signal, wherein a contribution of each of said plurality of delayed versions of said analog intermediate signal to said feedback signal is determined by a respective weight value;
- a first detector configured to recover a digital data sample from said analog intermediate signal in response to a clock signal;
- and
- a second detector configured to recover a sample of a zero crossing of said analog intermediate signal in response to said clock signal.
A method of adaptation of a delay line decision feedback equalizer comprising the steps of:
- generating an analog intermediate signal in response to an analog input signal and a feedback signal;
- generating a plurality of delayed versions of said analog intermediate signal;
- generating said feedback signal in response to said plurality of delayed versions of said analog intermediate signal, wherein a contribution of each of said plurality of delayed versions of said analog intermediate signal to said feedback signal is determined by a respective weight value;
- and
- recovering a data sample from said analog intermediate signal in response to a clock signal.
Dependencies are inferred from the claim text.