Silicon carrier optoelectronic packaging

An optoelectronic (OE) package or system for semiconductor fabrication, comprising:

• a silicon layer with wiring, the silicon layer defining at least one optical via for allowing light to pass therethrough;
• an optical coupling layer bonded to the silicon layer, the optical coupling layer including a plurality of microlenses for focusing and or collimating the light through the optical via;
• a plurality of OE elements coupled to the silicon layer and electrically communicating with the wiring, at least one of the OE elements positioned in optical alignment with the optical via for receiving the light;
• a carrier for interposing between electrical interconnect elements, the carrier positioned between the wiring of the silicon layer and a circuit board and the carrier electrically connecting first interconnect elements connected to the wiring of the silicon layer and second interconnect elements connected to the circuit board;
• and
• a thermal sink interposer positioned over the OE elements, said carrier including an alignment frame bonded thereto, said alignment frame including an alignment feature for positioning the carrier in mating relation with the optical coupling layer, said carrier laterally conducting heat from said silicon layer to the thermal sink interposer via said alignment frame.

A method for assembling or packaging a semiconductor or chip, comprising:

• fabricating a silicon layer with wiring, the silicon layer defining at least one optical via for allowing light to pass therethrough;
• bonding an optical coupling layer to the silicon layer, the optical coupling layer including a plurality of microlenses for focusing and or collimating the light through the optical via;
• coupling a plurality of OE elements to the silicon layer and the OE elements electrically communicating with the wiring;
• positioning at least one of the OE elements in optical alignment with the optical via for receiving the light;
• interposing a carrier between electrical interconnect elements, and positioning the carrier between the wiring of the silicon layer and a circuit board and electrically connecting first interconnect elements to the wiring of the silicon layer and second interconnect elements to the circuit board;
• and
• positioning a thermal sink interposer over the OE elements, and
• bonding an alignment frame to said carrier, said alignment frame including an alignment feature for positioning the carrier in mating relation with the optical coupling layer, wherein said carrier laterally conducts heat from said silicon layer to the thermal sink interposer via said alignment frame.