Turbo decoder

A wireless receiver comprising:

• a plurality of decoder circuits, including a first decoder circuit and a second decoder circuit, operative to decode in parallel encoded data blocks comprising a first set of data blocks and a second set of data blocks that are received by the wireless receiver;
• a plurality of non-overlapping memory banks, wherein each memory bank of the plurality of memory banks is in communication with the first decoder circuit and the second decoder circuit of the plurality of decoder circuits, the first set of data blocks and the second set of data blocks having memory addresses associated with the plurality of non-overlapping memory banks;
• a first plurality of buffers associated with a first memory bank of the plurality of memory banks;
• a second plurality of buffers associated with a second memory bank of the plurality of memory banks;
• a sorting circuit configured to:
• receive the decoded first set of data blocks from the first decoder circuit and the second set of data blocks from the second decoder circuit;
• selectably communicate the decoded first set of data blocks and the decoded second set of data blocks to the first plurality of buffers and the second plurality of buffers depending on the memory addresses of the first set of data blocks and the second set of data blocks;
• and a routing circuit configured to:
• communicate at least one data block of the decoded first set of data blocks or at least one data block of the decoded second set of data blocks from the first plurality of buffers to the first memory bank;
• and
• communicate at least one data block of the decoded first set of data blocks or at least one data block from the decoded second set of data blocks from the second plurality of buffers to the second memory bank;
• and
• a processor configured to receive the first data block from the first memory bank and systematically process the first data block through a systematic iteration.

A method comprising:

• receiving an encoded data block and dividing the encoded data block into a plurality of data blocks, including a first data block and a second data block;
• systematically processing, using a first decoding processor and a second decoding processor connected in parallel, the first data block and the second data block;
• assigning to the first data block of encoded data a first address within a first memory bank that is within a plurality of non-overlapping memory banks;
• assigning to the second data block of encoded data a second address within a second memory bank that is within the plurality of non-overlapping memory banks;
• sorting the decoded first data block to a first queue associated with the first memory bank or a second queue associated with the second memory bank;
• sorting the decoded second data block to the first queue or the second queue;
• reading the first data block from the first queue or the second queue and writing the first data block to the first memory bank or the second memory bank depending on the first data block sorted in the first queue or the second queue;
• reading the second data block from the first queue or the second queue and writing the second data block to the first memory bank or the second memory bank depending on the second data block sorted in the first queue or the second queue;
• and
• reading the first data block or the second data block from the first memory bank;
• and
• processing the first data block and the second data block through a systematic iteration.

An apparatus comprising:

• a plurality of decoding processors connected in parallel, including a first decoding processor and a second decoding processor, the plurality of decoding processors being configured to process, by decoding in parallel, a first data block of encoded data and a second data block of encoded data through a systematic iteration;
• a first interleaver configured to assign to the first data block of encoded data a first address within a first memory bank within a plurality of memory banks or a second address within a second memory bank within the plurality of memory banks, wherein the plurality of memory banks are internal to a single memory module;
• a second interleaver configured to assign to the second data block of encoded data a second address within the first memory bank or the second memory bank;
• a sorter configured to sort the decoded first data block to a first plurality of queues associated with the first memory bank;
• and to sort the decoded second data block to a second plurality of queues associated with the second memory bank;
• and
• a router configured to read the decoded first data block from the first plurality of queues and communicate the first data block to the first memory bank;
• and
• a processor configured to process the decoded first data block and the second data block through a subsequent systematic iteration.