Routing packets in on-chip networks
AssigneeEmpire Technology Development LLC
InventorWilliam H. Mangione-Smith
Life of this patent
Estimating the term…
Abstract
Techniques for packet routing in an on-chip network are provided. In one embodiment, a method for routing packets in a multi-core processor including multiple cores connected by an on-chip network includes identifying ports that are incorrect while routing the packet. After receiving the packet at an input port, some of the ports are excluded from consideration while selecting the output port for the packet. The output port is selected from the remaining ports and the packet is routed to the selected output port.
Claims21
A method to route packets in a multi-core processor, the multi-core processor including a plurality of cores coupled by an on-chip network, the method comprising:
- receiving a packet at an input port of a core included in the plurality of cores, the core including a processor and a network switch;
- excluding first ports of a plurality of ports of the core from consideration as potential output ports for the packet based on a previous output port of a previously received packet, the plurality of ports including the previous output port;
- selecting an output port for the packet from second ports of the plurality of ports based on a determination that the second ports are remaining for consideration as potential output ports for the packet after exclusion of the first ports from consideration as potential output ports for the packet;
- and
- routing the packet to the selected output port.
A method to route packets within an on-chip network of a multi-core processor, the multi-core processor including a plurality of cores that are coupled by the on-chip network, the method comprising:
- receiving a packet at a network switch of a core of a chip, wherein the network switch includes a plurality of ports and wherein the packet is to be routed to an output port included in the plurality of ports;
- identifying first ports from the plurality of ports based on a determination to exclude the first ports from consideration as potential output ports for the packet received at the network switch;
- selecting the output port from second ports included in the plurality of ports based on a determination that the second ports are remaining for consideration as potential output ports for the packet after exclusion of the first ports from consideration as potential output ports for the packet and based on a frequency of the output port acting as a previous output port for previously received packets;
- and
- routing the packet to the selected output port.
A multi-core processor comprising:
- a plurality of processor cores, at least one core including:
- a processor;
- a cache;
- a plurality of ports;
- and
- a network switch configured to route a packet received at a first port of the plurality of ports to a second port of the plurality of ports selected as an output port of the packet, the network switch further configured to select the second port from the plurality of ports when the packet arrives at the first port and based on a determination that the second port is included in a set of ports of the plurality of ports that remain for consideration as potential output ports for the packet after exclusion of one or more ports of the plurality of ports from consideration as potential output ports for the packet, the exclusion of the one or more ports from consideration being based on a previous output port of a previously received packet, the plurality of ports including the previous output port.
Dependencies are inferred from the claim text.