Method of operating semiconductor memory device with floating body transistor using silicon controlled rectifier principle

A semiconductor memory cell comprising:

• a floating body region configured to be charged to a level indicative of a state of the memory cell;
• a first region in electrical contact with said floating body region;
• a second region in electrical contact with said floating body region and spaced apart from said first region;
• a gate positioned between said first and second regions;
• a buried layer region in electrical contact with said floating body region, below said first and second regions, spaced apart from said first and second regions;
• and
• a substrate region configured to inject charge into said floating body region, wherein:
• said substrate region, said buried layer region, said floating body region, and either of said first or second regions form a silicon controlled rectifier device.

A semiconductor memory array comprising:

• a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein each said semiconductor memory cell includes:
• a floating body region configured to be charged to a level indicative of a state of the memory cell;
• a first region in electrical contact with said floating body region;
• a second region in electrical contact with said floating body region and spaced apart from said first region;
• a gate positioned between said first and second regions;
• a buried layer region in electrical contact with said floating body region, below said first and second regions, spaced apart from said first and second regions;
• and
• a substrate region configured to inject charge into or extract charge out of said floating body region to hold said state of the memory cell.