Precharging circuit and semiconductor memory device including the same
AssigneeHynix Semiconductor Inc.
InventorSeung-Bong Kim
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device includes a write driver for transmitting data loaded on a global line to a local line pair, a read driver for transmitting data loaded on the local line pair to the global line, a core region for storing data loaded on the local line pair or provide stored data to the local line pair, and a precharging circuit configured to precharge the local line pair by selectively using a first voltage and a second voltage in response to a precharge control signal and an operation mode signal, wherein the second voltage is lower than the first voltage.
Claims29
A precharging circuit comprising:
- a voltage selection providing unit configured to selectively provide a first voltage and a second voltage in response to an operation mode signal, wherein the second voltage is lower than the first voltage;
- and
- a precharging unit configured to precharge an input/output line pair with the selected voltage provided from the voltage selection providing unit in response to a precharge control signal,
- wherein different logic levels of the operation mode signal indicate a read operation mode and a write operation mode, respectively.
A semiconductor memory device comprising:
- a write driver configured to transmit data loaded on a global line to a local line pair;
- a read driver configured to transmit data loaded on the local line pair to the global line;
- a core region configured to store data loaded on the local line pair or provide stored data to the local line pair;
- and
- a precharging circuit configured to precharge the local line pair by selectively using a first voltage and a second voltage in response to a precharge control signal and an operation mode signal, wherein the second voltage is lower than the first voltage.
A precharging circuit comprising:
- a precharging control unit configured to receive a precharge signal according to an operation command and output a precharge control signal by restricting a toggling period of the precharge signal in response to a operation mode signal;
- and
- a precharging unit configured to precharge an input/output line pair in response to the precharge control signal.
A semiconductor memory device comprising:
- a write driver configured to transmit data loaded on a global line to a local line pair;
- a read driver configured to transmit data loaded on the local line pair to the global line;
- a core region configured to store data loaded on the local line pair or provide stored data to the local line pair;
- and
- a precharging circuit configured to restrictively precharge the local line pair in response to a precharge signal, an operation mode signal, and a data mask signal.
Dependencies are inferred from the claim text.