Memory circuit and method of writing datum to memory circuit

A circuit comprising:

• a first node configured to carry a first voltage;
• a second node configured to carry a second voltage less than the first voltage;
• a memory cell coupled to the first power node and the second power node and powered by the first voltage and the second voltage;
• a first data line and a second data line coupled to the memory cell;
• a write data line;
• a complementary write data line;
• a first N-type transistor having a source terminal, a drain terminal, and a gate terminal, the drain terminal of the first N-type transistor coupled to the first data line, the source terminal of the first N-type transistor coupled to the write data line;
• a second N-type transistor having a source terminal, a drain terminal, and a gate terminal, the drain terminal of the second N-type transistor coupled to the second data line, the source terminal of the first N-type transistor coupled to the complementary write data line;
• and
• a write signal driver coupled to a write data input terminal, a complementary write data input terminal, the write data line, and the complementary write data line,
• the first N-type transistor, the second N-type transistor, and the write signal driver being configured to selectively charge or discharge, in response to signals at the write data input terminal and the complementary write data input terminal, one of the first and second data lines toward a third voltage, less than the first voltage, and the other one of the first and second data lines toward the first voltage.