Semiconductor memory device capable of correcting the offset voltage of a sense amplifier

A control method for a semiconductor memory device including

• a plurality of memory cells arranged in a matrix,
• a plurality of word lines arranged corresponding to each row of the memory cells,
• a plurality of bit line pairs arranged corresponding to each column of the memory cells,
• a column selector that selects any of the plurality of bit line pairs based on a column selection signal and connects the selected bit line pair to a data line pair,
• a precharge circuit that precharges the data line pair,
• a sense amplifier that amplifies a potential difference of the data line pair, and
• a control circuit that controls current for driving the sense amplifier, the method comprising:
• precharging the data line pair to a specified potential by the precharge circuit;
• starting amplification of a potential difference of the precharged data line pair by the sense amplifier;
• detecting potentials of the data line pair after a lapse of a specified period from start of amplification of the potential difference of the data line pair by the sense amplifier by the control circuit;
• and
• controlling the current for driving the sense amplifier based on the potentials of the data line pair after a lapse of the specified period detected by the control circuit.