Clamped bit line read circuit

A memory array, comprising:

• a bit line;
• a storage cell that coupled to the bit line and is read when a word line is enabled;
• and
• a clamping circuit coupled to the bit line and configured to hold the bit line at a nearly constant clamp voltage during a read operation wherein the nearly constant clamp voltage is maintained through multiple inverters that are coupled in series between the bit line and first terminal of a resistor, wherein an opposing terminal of the resistor is coupled to the bit line.

A method of reading a bit line of a memory array, comprising:

• enabling a word line to perform a read operation of a storage cell;
• amplifying a change in current developed on a bit line that is coupled to the storage cell while the word line is enabled and while the bit line is held to a nearly constant clamp voltage by a clamping circuit, wherein the nearly constant clamp voltage varies by less than 50 millivolts during the read operation;
• and
• sampling an amplified voltage generated by the clamping circuit.

A method of reading a bit line of a memory array, comprising:

• enabling a word line to perform a read operation of a storage cell;
• amplifying a change in current developed on a bit line that is coupled to the storage cell while the word line is enabled and while the bit line is held to a nearly constant clamp voltage by a clamping circuit, wherein the nearly constant clamp voltage is maintained through multiple inverters that are coupled in series between the bit line and first terminal of a resistor, wherein an opposing terminal of the resistor is coupled to the bit line;
• and
• sampling an amplified voltage generated by the clamping circuit.