US 8,559,243 B2 · Self timed current integrating scheme employing level and slope detection

Abstract

Some embodiments of the invention relate to a sense amplifier configured to determine the slope of a bitline charging voltage and to utilize the determined slope in combination with a voltage level sensing scheme to aid in reading data from a memory cell associated with the bitline. In particular, a sense amplifier circuit is configured to determine a slope of a bit line charging voltage and based upon the determined slope to adjust the slope of the bitline voltage (e.g., by adding a dynamic slope dependent current to a memory cell current configured to charge the bitline) provided to a sense amplifier. By adjusting the slope of the bitline voltage, the charging speed of memory cells in a low resistive state (e.g., having a high cell current and therefore a good SNR) can be increased.

Claims21

Dependent claims

A memory circuit, comprising:

a memory cell configured to generate a memory cell current that provides charge to an associated bitline, wherein the charge increases on the bitline as a function of time to generate a bitline voltage having a slope;
a slope detection component coupled to the bitline and configured to detect the slope of the bitline voltage associated with a read operation of the memory cell within a resistive state, and to enhance the slope of the bitline voltage during the read operation based upon the resistive state of the memory cell;
and
a level detection component configured to detect a voltage level of the bitline and to generate a sense amplifier output signal when the bitline voltage is greater than a threshold voltage level.

1 more element

A sense amplifier circuit comprising, comprising:

a slope detection component configured to determine the slope of a bitline voltage during a read operation of a memory cell within a resistive state and to selectively increase the slope of the bitline voltage if the determined slope corresponds to a high resistive state of a memory cell being read to increase a charging speed of bitline;
and
a level detection component configured generate a sense amplifier output signal when the bitline voltage is greater than a threshold voltage level;
wherein enhancing the slope of the bitline decreases a time expended for the bitline to reach the threshold voltage level.

1 more element

Dependencies are inferred from the claim text.

Self timed current integrating scheme employing level and slope detection

Life of this patent

Self timed current integrating scheme employing level and slope detection

Life of this patent

Abstract

Claims21