Data receiver, semiconductor device and memory device including the same
AssigneeSamsung Electronics Co., Ltd.
InventorsSung-Joo Park, Jea-Eun Lee, Jung-Joon Lee, Yang-Ki Kim, Kyoung-Sun Kim
Life of this patent
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Abstract
A data receiver includes a first buffer circuit and a second buffer circuit. The first buffer circuit varies a resistance of a data path and a resistance of a reference voltage path based on a plurality of control signals, and adjusts a voltage level of an input data signal and a level of a reference voltage to generate an internal data signal and an internal reference voltage based on the varied resistance of the data path and the varied resistance of the reference voltage path. The second buffer circuit compares the internal data signal with the internal reference voltage to generate a data signal.
Claims20
A data receiver comprising:
- a first buffer circuit configured to vary a resistance of a data path and a resistance of a reference voltage path based on a plurality of control signals, and configured to adjust a voltage level of an input data signal and a level of a reference voltage to generate an internal data signal and an internal reference voltage based on the varied resistance of the data path and the varied resistance of the reference voltage path;
- and
- a second buffer circuit configured to compare the internal data signal with the internal reference voltage to generate a data signal.
A semiconductor device comprising:
- a control circuit configured to generate a plurality of control signals;
- a first buffer circuit including:
- a first variable resistor circuit to generate a first variable resistance, the first variable resistor circuit configured to receive an input signal through an input terminal and to pass the input signal through the first variable resistance to generate a first internal signal in response to at least one of the control signals;
- and
- a second variable resistor circuit to generate a second variable resistance, the second variable resistor circuit configured to receive a reference voltage through a reference voltage terminal and to pass the reference voltage through the second variable resistance to generate a first internal reference voltage in response to at least one of the control signals,
- a second buffer circuit configured to receive the first internal signal and the first internal reference voltage to generate an output signal.
A memory device comprising:
- an input terminal to receive an input signal external to the memory device;
- and
- a buffer circuit comprising:
- a first buffer circuit including a plurality of resistors to generate a first variable resistance, the first buffer circuit connected to the input terminal and configured to receive the input signal and output an internal signal through the first variable resistance in response to a plurality of control signals;
- a second buffer circuit configured to receive the internal signal and to generate an output signal;
- and
- a control circuit configured to generate the plurality of control signals to select the first variable resistance.
Dependencies are inferred from the claim text.