Sense amplifying circuit, and semiconductor memory device having the same

A CMOS latch-type sense amplifying circuit, comprising:

• a first stage amplifier configured to amplify a voltage signal of an input line pair to generate a first amplified voltage signal pair, and provide the first amplified voltage signal pair to a first line pair, a first pre-charge voltage having a first voltage level being applied to the input line pair;
• a second stage sense amplifier configured to amplify a voltage signal of the first line pair to generate a second amplified voltage signal pair, and provide the second amplified voltage signal pair to the first line pair;
• a switch circuit coupled between the first line pair and an output line pair, configured to electrically couple the first line pair to the output line pair in response to a first switch control signal, a second pre-charge voltage having a second voltage level different from the first voltage level being applied to the output line pair;
• and
• a first common node controlled by a second switch control signal and connected to both the first stage amplifier and the second stage sense amplifier, such that the second switch control signal controls both the first stage amplifier and the second stage sense amplifier.

A semiconductor memory device, comprising:

• a memory core coupled to a bit-line pair;
• a column selecting circuit configured to output voltage signals of the bit-line pair to a local input/output line pair in response to a column selecting signal;
• a CMOS differential amplifier including PMOS and NMOS transistors, the CMOS differential amplifier configured to receive a first set of voltage signals of the local input/output line pair, and output a second set of voltage signals to a first line pair;
• a CMOS latch-type sense amplifier configured to amplify the second set of voltage signals of the first line pair, and output a third set of voltage signals to the first line pair;
• a global selecting circuit configured to output voltage signals of the first line pair to a global input/output line pair in response to a global selecting signal;
• an input/output sense amplifying circuit configured to amplify the voltage signals output from the global selecting circuit;
• and
• an output buffer configured to receive voltage signals output from the input/output sense amplifying circuit and output an output voltage signal to an output line,
• wherein the voltage signals of the local input/output line pair are electrically separated from the voltage signals output from the global input/output line pair, such that interference on the first set of input signals is reduced.