Semiconductor memory device

A semiconductor memory device comprising:

• a memory cell array that has memory cells each connected to a word line and a bit line;
• a first detecting circuit that outputs a first detection signal which shows whether an externally supplied external power supply is equal to or more than a first voltage;
• a second detecting circuit that outputs, at a higher speed than the first detecting circuit, a second detection signal which shows whether the external power supply is equal to or more than the first voltage;
• a switching circuit, wherein in a write operation that applies a write voltage to a word line connected to the memory cell, the switching circuit outputs the second detection signal that is output from the second detecting circuit, and in an operation other than the write operation, the switching circuit outputs the first detection signal that is output from the first detecting circuit;
• and
• a recovery control circuit that terminates the write operation according to the second detection signal that is output from the switching circuit.