Sense operation in a stacked memory array device
AssigneeMicron Technology, Inc.
InventorsAkira Goda, Zengtao Liu
Life of this patent
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Abstract
One method for sensing includes changing a sense condition of a particular layer responsive to a programming rate of that particular layer (e.g., relative to other layers). In one embodiment, the target threshold voltage range can be shifted lower for a slower programming layer. This might be accomplished by biasing the bit lines of slower programming layers with higher bit line voltages as compared to bit line voltages of faster programming layers.
Claims21
A method for sensing a plurality of layers of memory cells, the method comprising:
- changing a sense condition of a particular layer of the plurality of layers of memory cells responsive to a programming rate of the particular layer;
- wherein each of the plurality of layers comprises a separate source line and wherein the sense condition comprises biasing each of the separate source lines with a respective source line voltage responsive to a programming rate of a respective layer comprising the source line biased with the respective source line voltage.
A method for sensing a plurality of layers of a stacked memory array architecture, the method comprising:
- programming the plurality of layers of the stacked memory array;
- and
- changing a sense condition of a slower programming layer of the plurality of layers relative to a faster programming layer of the plurality of layers;
- wherein each of the plurality of layers comprises a separate source line and wherein the sense condition comprises biasing each of the separate source lines with a respective source line voltage responsive to a programming rate of the respective layer.
A method for sensing a plurality of layers of a stacked memory array architecture, the method comprising:
- programming the plurality of layers of the stacked memory array;
- and
- changing a sense condition of a faster programming layer relative to a slower programming layer;
- wherein a separate source line is coupled to a particular group of layers of the plurality of layers and wherein changing the sense condition comprises biasing the separate source line with a respective source line voltage responsive to a programming rate of the particular group of layers.
A memory device comprising:
- a plurality of layers of memory cell arrays, each layer comprising:
- a plurality of series strings of memory cells, each series string including a select gate source transistor on a first end and a select gate drain transistor on an opposing end;
- a separate source line that is different from source lines that are coupled to other layers of the plurality of layers;
- a select gate source line coupled to control gates of each of the select gate source transistors of each of the plurality of layers;
- a plurality of select gate drain lines, each select gate drain line coupled to control gates of the select gate drain transistors of a different one of the plurality of layers;
- and
- a plurality of access lines, each access line coupled to a respective row of memory cells of each layer;
- wherein the memory device is configured to select a respective layer using a respective one of the select gate drain lines and to bias a selected one of the access lines with a sense voltage that includes an offset voltage responsive to the respective layer having a different programming rate, relative to a programming rate of another one of the layers.
Dependencies are inferred from the claim text.